Beverly, MA (June 04, 2001) -- Improv Systems Inc., a pioneer in configurable DSPs for communications and media, today introduced its Jazz 2 architecture and its accompanying family of Jazz 2 configurable processor core tool suites. The second-generation version of the company’s popular Jazz processor core offers a 16-bit option to complement its existing 32-bit architecture, introducing lower power dissipation and smaller die size core solutions. Jazz 2 also features new support for designing with legacy microprocessor host solutions such as ARM’s AMBA/AHB bus and MIPS PI bus interfaces.

The Jazz 2 Standard Tool Suite 2.0 release targets application software development utilizing Integrated Development Environment (IDE) tools from leading suppliers such as Borland, Symantec (now Webgain), IBM and Motorola and incorporates its latest release of the Jazz 2 Compiler. In the release of its Performer Tool Suite 2.0, a HW/SW CoDesign environment, Improv has incorporated an automated processor configuration tool (Jazz Composer 2), that produces customized Jazz 2 processors in under an hour. With a single Jazz 2 processor foundation, designers can now quickly and easily configure an Improv-based system to address a wide spectrum of applications and system-on-chip (SOC) designs requiring DSP functionality.

Market researchers have pegged the DSP market as the fastest growing and largest processor market segment, and Jazz 2 significantly expands Improv’s coverage of the DSP market space over the initial Jazz product offering. The wide price/performance needs, as well as the diverse market requirements in the communications sectors, make Improv’s configurable methodology an ideally suited approach from a time, cost and efficiency standpoint.

"Improv truly has one of the most scalable DSP solutions available today," commented Will Strauss, president of Forward Concepts. "The Jazz 2 architecture, coupled with Improv's novel HW/SW design methodology and tool chain, makes this configurable VLIW processor an attractive option for a wider range of DSP applications than possible with a fixed configuration."

The new 16-bit processor architecture in Jazz 2 is specifically aimed at applications that require efficient power consumption and smaller footprints, such as wireless and mobile products. The 16-bit option complements the 32-bit version of Jazz, which targets high-performance applications such as media and network processing. Enhancements in code compression, processor architecture and memory utilization enable advanced power management features and streamlined silicon implementation with Jazz 2. The enhancements also allow designers to target more advanced process technologies, such as 0.13 micron and beyond, as well as higher clock speeds (e.g. 200 MHz).

"Our initial version of Jazz and our configurable methodology do an excellent job of targeting very high-end applications. With this new version, we are expanding the applicability of the configurable DSP approach to a wider range of design needs without compromising the performance of the core or the efficiency of the methodology," said Cary Ussery, President and CEO of Improv Systems. "In fact, the enhancements we have made to our tool suite benefit our entire Jazz family and make our solution that much easier to use."

The Jazz 2 family comes with a set of pre-designed versions of the Jazz processor core, ranging from a single-MAC (Jazz 2010), to a dual-MAC (Jazz 2020), to a quad-MAC version (Jazz 2040). Jazz 2010 is suited for entry-level applications and provides performance suitable for motor control, servo, and audio applications with a gate count as low as 50K gates. Jazz 2020 is aimed at the bulk of the current DSP market as well as emerging applications such as VoIP, streaming video and encryption, providing over 400 Million Multiply ACcumulates (MMACs) of DSP performance with a gate count of 125K gates. Jazz 2040 is geared for higher-end applications such as broadband, central office and media processing, providing 800 MMACs of DSP performance with a gate count of 175K gates. These processors, like all Jazz configurations, can be used as standalone DSP cores or combined into efficient multi-processor platforms with multiple Jazz DSP cores and ARM or MIPS host processors. Provided as Verilog source code, these standard configurations of Jazz processor cores offer equivalent price/performance to a wide range of traditional standalone DSP products, while retaining the ability to be easily optimized to meet domain or product specific requirements.

Designers can begin a development project with any of the standard Jazz processor configurations, and then use Improv’s configurable methodology and tool suite to customize their system for specific market requirements. The Jazz development environment includes intuitive design and debugs tools, advanced compilation technology, and optional application software optimized for the Jazz architecture.

Jazz 2 also includes a complete set of configurable integration blocks that enable rapid integration into an overall SOC design. Customized bus interface blocks allow the Jazz 2 to be easily linked to legacy platforms based on popular processor cores such as those from ARM and MIPS. Improv offers development kits and Rehearsal cards for each of those device families, allowing designers to develop and test application code and run SOC simulations on the combination of the processors.

Pricing and Availability

The Jazz 2 Processor and associated Jazz 2 tool suites are available immediately. Existing customers receive upgrade releases of the Jazz 2 Processor & associated Standard and Performer Tool Suites as a standard component of their licensing agreements. Design Seats for the Jazz 2 Standard Tool suite begin at <$5K/seat. Please contact the factory regarding details of the Jazz 2 Performer Tool Suite and Jazz 2 Processor Core licensing fees and royalties.

About Improv Systems, Inc.

Improv Systems, Inc. develops and licenses configurable DSP processors and platform solutions for Voice-over-IP, Networking and Emerging Media. Improv’s Jazz DSP is a programmable, scaleable, and configurable DSP, targeted to consumer electronics and telecommunications markets. Improv’s solution extends beyond the hardware; it includes a complete tool suite to facilitate rapid, system level design and state-of-the-art compilation technology to efficiently map applications onto its Jazz DSP solution. In addition, Improv offers pre-designed applications platforms for a complete solution and software components to jump start product development efforts. Improv Systems has development centers in Beverly, MA, Santa Clara, CA, and Rochester, NY, and direct sales offices in Paris and Tokyo. Improv is headquartered in Beverly, MA (01915) at 100 Cummings Center Suite 343G and can be reached at (978) 927-0555 or at www.improvsys.com.

Anyone watching the stock market and keeping an eye on firms such as Lucent and Cisco, knows that sales of high-end routers and other units of that class have slowed considerably. As a result, companies selling into those markets for sophisticated, powerful media and video packet processing have likewise seen their sales drag. On the other hand, walk down the street and look at all the kids and adults playing with their new electronic toys, whether cell phones, music players or even portable DVD players. Chip vendors selling into those markets are much more optimistic about prospects for both the near as well as distant future.

OEMs have also found that they don’t have to turn to standard parts as they have in the past. They can now program ASICs or FPGAs to perform specific tasks, and sometimes they turn to programmable cores to create an architecture optimized specifically for a narrow-niche, high-volume product. "Our industry needs application-specific chips," says Improv president Cary Ussery, "and we’re the first to come out with an architecture, methodology and toolchain specifically optimized for a software-configurable architecture." "The closest thing to it," he adds, "might come from StarCore, but there you don’t have the freedom to use any foundry as you do with Improv’s designs."

Improv’s approach to this market has a history that deviates somewhat from the usual progression. Generally chip suppliers start with a low-end device and move up the price/performance scale with successive generations. However, in this case, and in consideration of market conditions, Improv is taking the opposite approach. At the start of last year the firm introduced its original Jazz architecture, targeted at high-end media and video processing. But now with Jazz2, it hopes to get some business for its configurable cores in the consumer, low-power, single-processor designs.

Most noticeably at first glance, Jazz2 drops down from being a 32-bit to a 16-bit architecture. A key feature is the addition of extensible computation units, which perform designer-specific sets of opcodes. Note that with the original Jazz architecture you could run multiple "slots" in parallel, with each slot consisting of an ALU, MAC, DDCU (designer defined computational unit) or Shift block. However, once you assigned the order for each slot, it remained fixed. With the Jazz2 architecture, however, the programmer can mix the type and order of these function blocks for each slot on a per-cycle basis, giving you extreme flexibility.

Also interesting for consumer applications are the OEM-selectable low-power modes and power-management techniques inside the processor. For instance, to save power you can activate automatic gating of elements not being used.

The firm also boasts of improved code density thanks to compression, instruction-slot assignment and instruction packing. The company president, Cary Ussery, believes that this architecture is equivalent to a RISC DSP.

The toolchain is also something of which the company is proud. It includes profiling so you can evaluate the utilization of hardware for application code, and the firm claims that it automates the cycle time for a designer to develop a custom processor to < 1 hour. The Jazz2 Performer Toolsuite 2.0 actually consists of three tools: with the first, you can work with your own computational units to create unique opcodes (instruction extensions) and datapaths (execution extensions); next, users can create complete processors; third, they can also create multiprocessor cores. In this regard, Improv has agreements that let users work with cores from both MIPS and ARM for those applications that require both DSP and microcontroller functionality.

The architecture is far enough along, he adds, that the firm has already done ten tapeouts, most at 0.18 microns, one at 0.25 with work progressing on 0.13.