The manufacturer says . . .

ChipCenter's Paul Schreier says . . .

Santa Clara, CA--August 12, 2002--DSP Group Inc., the world leader in the development and licensing of DSP cores, unveiled CedarDSPCore, a new licensable high-performance and low-power architecture. The CedarDSPCore is a scalable and extendible architecture with various DSP core designs for different cost and performance metrics. It is targeted at a broad range of markets and applications such as Communication Terminals—e.g., 3G smartphones, 802.11a/b/g terminals, and access points and broadband modems; Infrastructure—e.g., base stations, media gateways, and DSLAMS; and Home Entertainment—e.g., DVD recorders, PVRs, and set-top boxes. "Once again, DSP Group is offering an exciting new high-performance DSP architecture," commented Will Strauss, president of market research firm Forward Concepts. "The new scalable architecture allows the CedarDSPCore to be employed across a broad product line from mid-performance to very high performance applications while offering extendibility for product differentiation. Coming from a company with established leadership in DSP licensing, this powerful architecture will keep DSP Group as the team to beat." DSP Group's CedarDSPCore presents a unique mix of features designed to benefit its licensees in three main areas: scalability, productivity, and extendibility. Scalable Performance at Low Energy Consumption Performance scalability allows CedarDSPCore licensees to develop software-enabled products for infrastructure, wireless, and multimedia emerging markets. Combining Very Long Instruction Word (VLIW) and Single-Instruction Multiple Data (SIMD) technologies, the CedarDSPCore offers operating speeds up to 450 MHz (0.13 µm worst case process in a synthesizable form) with scalable computation capability such as 2 to 8 multiply-accumulates (MACs) in a clustered model. Furthermore, the scalability runs deeper than MACs as each cluster includes several arithmetic and logical units and a large register file. Using four such clusters results in a high-performance architecture that executes numerous parallel operations in a single cycle. A scalable number of clusters with scalable memory bandwidth and different data native words create various core versions with a different mixture of performance-cost-energy consumption metrics. Productivity Programming in high-level languages such as C or C++ and the use of compilers for optimization significantly shortens the software development process and reduces time-to-market cycles. The CedarDSPCore architecture incorporates dedicated compiler-oriented mechanisms to increase compiler optimization that result in a powerful compiler for the CedarDSPCore. The hardware implementation of CedarDSPCore, as in the previous SmartCores series, has been designed from the ground up as a fully synthesizable model, also known as a "soft core." This provides users a short turnaround cycle when migrating between existing processes and silicon foundries. The CedarDSPCore is delivered with a complete and advanced set of software and hardware development tools. Extendibility The growing adoption of industry standards for high-volume applications such as wireless LAN (802.11a/b/g) or cellular communications (WCDMA, UMTS) creates a challenge for IC vendors as they attempt to differentiate their products and provide added value. The CedarDSPCore gives licensees the flexibility to extend the architecture through adding user-proprietary extension units to create value-added features while maintaining the benefits of an open, fully verified, widely used architecture. "The CedarDSPCore architecture will broaden our market presence to new applications such as infrastructure, software-enabled wireless modems, and home entertainment," said Bat Sheva Ovadia, VP Marketing and Business Development at DSP Group's Technology Licensing Division. "Our significant installed base of TeakLite, Teak, and PalmDSPCore licensees, as well as third-party partners, will find the CedarDSPCore technology an enabler for exploring additional opportunities, while taking advantage of legacy developments and relationships they have developed with DSP Group over the years," added Ms. Ovadia. "DSP Group is the world's largest licenser of DSP cores with more than a decade of experience in successful licensing," said Eli Ayalon, Chairman and CEO of DSP Group. "The CedarDSPCore's compelling set of features and performance demonstrates our long-term commitment to our customers and to the DSP market," added Mr. Ayalon.

The DSP Group has been making a number of announcements recently, so let's take a look at where this release of the CedarDSPCore falls into the grand scheme of things. First, though, I think that it's interesting how large this company has become since its founding in 1987. Last year's revenues were in excess of $114 million, and its income increased 38% year-over-year in its second quarter ended June 30. Of those revenues, $26.6 million came from the Technology Licensing Div., and 20% of those are from royalties. These numbers place the company in the top tier of competitors. Indeed, Gartner Dataquest ranks it #1 in licensed DSP cores for IP for 2001, with a 69% market share, and Forward Concepts ranks it #2 (following TI) in baseband chips for the digital cellular market. Although the firm might not be a household name, or a name on the tip of the tongue of every design engineer, it is becoming a force to be reckoned with. Within the Technology Licensing Div., the company has three major directions at various levels of integration. At the top are application solutions, represented by the OpenKey family introduced roughly 6 months ago. Here you get a hardware and software subsystem suitable for use as a block in a system-on-a-chip. The second branch is the XpertDSP family, which is roughly two months old. It consists of one of the firm's IP cores surrounded by peripherals and subsystems, and it is also available as a bonded-out core in a development board. The third fork represents the lowest level, that of the licensable cores themselves. Here the company refers to CedarDSPCore as being the sixth generation. The first two generations (PineDSPCore and OakDSPCore) are no longer being actively licensed. Third is TeakLite, which has a single MAC and offers performance adequate for 2G applications. Next came the dual-MAC Teak, intended for 2.5G apps. For 3G applications, the firm introduced the 5th generation in its family of cores, the PalmDSPCore with a dual and parallel MAC architecture. The new CedarDSPCore, actually a fork off of the PalmDSPCore path, goes a big step further because it is scalable and extendible. Thus it can tackle a broad range of markets thanks to a variety of cost and performance points. It also offers more power than ever before from a DSP Group core, prompting Bat-Sheva Ovadia, VP of marketing and business development, to comment that Cedar enlarges the firm's market into infrastructure applications. And even though it is so similar to the Palm core, Ovadia doesn't see the Cedar's low-end configurations cannibalizing the Palm's business any time soon; above all, it takes time for architecture to get known and accepted. As for scalability, the core can come with three native word sizes (16, 24, or 32 bits), and either two, four or eight MACs, always configured in clusters of two MACs. Note that a device with a single MAC is not an option in this family. The firm also touts low power consumption. For instance, it quotes a Cedar 1620 (16-bit word size with two MACs) running at 450 MHz at 0.08 mW/MMAC, or 72 mW for this core. Let's take a closer look at the cluster concept with the help of the block diagram at the top of the page. Each cluster contains two MACs, one ALU, one bit-manipulation unit, 16 accumulators, and three ASUs (arithmetic subtraction units) embedded in the multipliers and bit manipulator. So not only do all of these blocks run in parallel at the same clock speed, a chip with multiple clusters runs them all in parallel. This scalability allows engineers to find the level of performance needed for a given job, and they don't have to pay for a chip any larger than necessary to do it. Clearly, to access this power you need a corresponding powerful compiler, and it's not the kind of thing you'll expect to get from Microsoft or somewhere on the Web. The DSP Group is working to get a compiler ready for the first quarter of next year, and they're also working with third-party tool makers to encourage them to support the device.

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