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Milpitas, Calif.--Sept. 23, 2002--Extending the portfolio of its popular open-architecture ZSP digital signal processor cores, LSI Logic Corp. introduced the ZSP500, the industry's highest performance DSP for consumer multimedia and mobile applications. Based on the ZSP second-generation G2 superscalar architecture, the ZSP500 provides designers a powerful DSP platform with the best power and cost over performance combination in its class. "The current market requirements in consumer and wireless applications call for a low-power and low-cost DSP solution, yet maintaining the highest level of performance possible," said Will Strauss, president of market research firm Forward Concepts. "Code density is an important design criterion in the selection of embedded processors since memory size directly drives the system cost that is critical in high-volume applications. LSI Logic hits the market sweet spot with the ZSP500 and raises the bar in this application space." The ZSP500's architectural innovations include an eight-stage pipeline, scalable program and data paths, and user-configurable memory architecture, enabling clock speeds of up to 400 MHz in 0.11 µm technology. The addition of a richer instruction set produces better code density and a more efficient execution of key algorithms, resulting in the highest level of signal-processing performance among the licensable DSP cores available today. The ZSP500 provides customers with unprecedented customization, time-to-market, and cost advantages compared to conventional digital signal processors. It includes the most extensive embedded debugging capabilities for a DSP processor in its class, plus real-time profiling and an optional Embedded Trace Module (ETM) for advanced in-system multiprocessor hardware and software debugging. The ZSP500 core also allows designers to incorporate customized instructions for their target application. Customers can differentiate by adding their own acceleration logic onto a highly programmable, multi-processor platform for advanced multimedia and communications applications such as GPRS, CDMA2000, MPEG-4, and WLAN 802.11. The ZSP500 is available for use in LSI Logic's exciting new RapidChip semiconductor platform for fast SoC designs. "We've had tremendous success with the original ZSP superscalar architecture, licensed by Broadcom, IBM, Conexant, and other market leaders," said Tuan Dao, vice president of the LSI Logic DSP Products Division. "This core further strengthens the ZSP family and extends our offering to cover applications from low-end audio, voice-over-IP, to high-end wireless and telecommunications infrastructure. The ZSP DSP family is the only solution in the market available as licensable IP cores, ASIC cores, and standard products. The ZSP digital signal processor is a mature and proven technology. Customers can be confident they're on the path to winning in the market." The ZSP500 has been recently profiled in a detailed technical report available from Berkeley Design Technologies Inc., a leading independent provider of DSP processor analysis and consulting services. Based on the results of their industry-standard BDTI Benchmarks, BDTI has given the ZSP500 a BDTIsimMark2000 score of 2570 at 325 MHz. Their evaluation shows that the ZSP500 has class-leading speed. The BDTI report credits the ZSP500's speed to its remarkable flexibility: "The ZSP500 is a remarkably flexible architecture; for example, most ALU operations can execute on any of three ALUs, and can use any data registers as operands. In addition, most ZSP500 operations support both 16- and 32-bit data, which gives the ZSP500 better support for 32-bit precision than most DSP processors. The C-style operations are also notable, as they should improve compiler performance." The complete report on the ZSP500 is available now directly from Berkeley Design Technologies. LSI Logic's leading ZSP Solution Partners program supports the ZSP500, comprising the broadest third-party application and software portfolio in the licensable DSP market, as well as by the LSI Logic ZOpen development framework, simplifying code development and integration. In support of the ZSP500, Green Hills Software, First Silicon Solution, and a number of application-software providers will be offering a suite of tools and application-specific solutions to speed time-to-market. LSI Logic and FS2 Announce On-Chip Instrumentation and System Analyzer Tools for ZSP500 Next-Generation DSP Cores The first synthesizable core to offer built-in performance analysis features for eliminating execution bottlenecks and improving DSP algorithm performance Milpitas, Calif.--Sept. 23, 2002--LSI Logic Corp. and First Silicon Solutions announced the availability of the ISA-ZSP500 In-Target System Analyzer for debugging and testing designs using ZSP500 synthesizable DSP cores. The System Analyzer consists of FS2 On-Chip Instrumentation (OCI) IP that is licensed as an option with the LSI Logic ZSP500 synthesizable core. A hardware probe for communications with the target resident OCI IP and Windows-based control and display software complete the system. The system analyzer provides complete debug support for the ZSP-based target hardware, and is fully integrated into the PC host resident development software. The FS2 OCI IP provides a number of user-configurable options for collecting traces, allowing the user to optimize the system for available SoC resources. The system is unique in being able to capture program and data trace either on-chip or streaming data off-chip via a high-speed Mictor cable connection. The system also provides the first-ever hardware-based performance-monitoring system for profiling DSP resources and measuring code execution times. "The ISA-ZSP500 System Analyzer integrates functions that in the past would require an assortment of debuggers, logic analyzers, software programs, or simulation environments to perform. FS2's OCI IP enables these capabilities to be easily accessible for the synthesizable DSP core user at real-time system speeds," said Rick Leatherman, president of FS2. "The built-in performance-monitoring features allow the user to identify CPU resource bottlenecks and areas where software algorithms can be optimized for better performance." "LSI Logic is pleased to include FS2 in its expanding network of ZSP Solution Partners," said Tuan Dao, vice president of the LSI Logic DSP division. "FS2 is among our most innovative partners, providing leading-edge tools and quality support for product development. The ISA-ZSP500 is another example of how ZSP customers are not just getting a DSP, they're getting access to a complete solution that helps them accelerate their development efforts and reduce time-to-market." Hardware-Based Performance Monitoring The ZSP500 is a superscalar DSP that can execute up to four instructions per clock cycle. The OCI block provides three different performance measurement modes: The first is the unique Execution Profile Trace, which can capture the number of instructions executed on each clock cycle. This information is used to assist in reordering instructions to get more parallel execution from the core, which is particularly important to programmers optimizing tight algorithmic loops. The second measurement mode — A → B timers — provides precise timing of the duration between four execution address watch points. Being able to accumulate durations around a function call or a critical algorithm is extremely useful for finding and fixing performance bottlenecks. The third—performance monitoring—can count any of 26 different types of system characteristics, such as total instructions, specific instruction types, cache hits, pipeline stall cycles, and load-store occurrences. Useful ratios such as instruction, data loads, or interrupts per second, and cache hit/miss ratios can then be calculated. Pricing and Availability The ISA-ZSP System will be available in November, 2002. Pricing is $2,995 for the on-chip version, and $4,995 for the system with off-chip trace support.

Last fall, LSI Logic took a big step beyond the first-generation ZSP400 and introduced its initial second-generation product in the ZSP family, the ZSP600. That was the biggest leap in performance since 1998, when the 400 went into volume silicon production (for background info, ZSP was acquired by LSI Logic in 1999). The ZSP600 is a quad-MAC design running at speeds as high as 500 MHz, and with this amount of horsepower it's targeted at infrastructure applications. However, when it comes to the number of devices being sold, there's far more business to be had in portable multimedia appliances. With this announcement of the ZSP500, LSI is targeting this power- and cost-conscious segment. As for the future, LSI will say only that the family roadmap includes a third-generation ZSP, which you might expect some time in the 2004 timeframe. As with the ZSP600, LSI is very proud of the fact that this technology will be available in three ways: as a standard off-the-shelf product, as ASIC hard macros, and as licensable RTL intellectual property. In the case of the ZSP500, this initial announcement covers the IP version; you might expect the ASIC macros in the first quarter of next year, but the firm has not disclosed a schedule for the availability of standard products based on the 500. The ZSP500 is very similar to the 600, the primary difference being that it's a dual-MAC structure with a peak frequency somewhere between 250 and 400 MHz in a 0.13 µm process. The devices are so similar that they share the same instruction-set architecture, and the code is compatible in both directions. And it's not just compatible at the source level—a binary image that runs on one also runs unmodified on the other. Note that this doesn't hold true for the ZSP400, which is compatible at the assembly level, but not the binary level. To be more specific about differences between the ZSP500 and 600, senior IP licensing manager Steve Brightfield first repeats the fact that the 500 has two MACs feeding one ALU, while the 600 has a second set of dual MACS feeding a second ALU. Thus, when it comes to parallelism, the 500 can execute four instructions per clock cycle, whereas the 600 can execute six instructions. A final aspect concerns I/O bandwidth and data throughput—the two data paths from the ZSP's Load/Store unit that interface with an external memory controller are now each 32 bits wide instead of the 64 bits wide in the ZSP600. As noted earlier, one goal is lower power consumption. All the cores (400, 500, 600) feature software control at the core level to implement Idle, Sleep, and Powerdown modes. All the cores also feature block-level power control with pipeline logic, and offer advanced clock-gating techniques, static core, and IP that's targetable to low-power libraries. Unique to the 500, however, is a capability that LSI believes is a "first" in a licensable IP core—clock-by-clock powering of the execution or arithmetic units. This automatic hardware control is dynamically managed by an onboard scheduler, and allows the device to adapt power consumption to instruction and data flows. The result is that the chip can span a wide range of points on a plot of performance vs. power vs. cost (here, meaning die size). The example Brightfield gives is the execution of a vector dot product running continuously with no NOPS, so both the MACs and the ALU run every clock cycle. Using a low-power library and executing at 100 MHz, the ZSP500 requires a die 1.4 mm² (in a 0.13 µm TSMC process), and it draws 18 mW. With a standard library and execution at 250 MHz, the die size increases to 2.8 mm² and the power rises to 50 mW. Finally, running at 400 MHz with a high-speed library, the die size bumps up to 3 mm², but the power triples to 150 mW. When asked how these numbers might compare to the ZSP600, Brightfield estimates that you'd need roughly 50% to 100% more power dissipation, depending on the exact requirements. A point worth highlighting is that although the second-generation cores contain parallel computational blocks, programmers work with natural straight-line coding. A hardware scheduler in the DSP core looks ahead at instructions in the stack, examines them for parallelism, and then groups them accordingly. The 500/600 also extend the ANSI C instruction set with replicants of existing instructions, but they set the format of syntax and operands in a way that allows a compiler to do a better job of mapping the instructions into assembler commands, thereby improving code density. On the tools side, like the ZSP600, the 500 works either with LSI's internally created GNU SDK with an optimizing C compiler, shipping today, or with another SDK from Green Hills Software. That third-party tool gives engineers multicore debugging so they can better develop designs that contain cores from several suppliers such as LSI, MIPS, or ARM. Note, though, that the ZSP500 version of the Multi2000 product is yet in beta testing, and the production version should be ready by the end of the year. Likewise slated for the end of the year is a ZSP500 prototyping hardware board that combines the ZSP500 silicon with an FPGA for control of external resources plus a JTAG/Trace port. New for the first time with this release, though, is on-chip instrumentation available as both IP and an external pod that allows embedded-trace modeling with real-time trace collection, branch execution information, and examination of load/store addresses and data. This capability comes from First Silicon Solutions. That firm, based in Portland, Oregon, was founded in 1998, and current adopters of FS2 tools include National Semiconductor, MIPS Technologies, Mentor Graphics, and Zilog. Some background information about FS2's debugging technology is available at www.eetimes.com/story/OEG20001218S0037.

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