DSP

Today's Feature

Memory Techniques Lead the Way to Optimizing DSP Applications—Part 2: DSP Program Optimization by Rob Oshana, Texas Instruments
This article is the second of a two-part series that summarizes some of the techniques used to gain orders-of-magnitude speed increases from high-performance DSPs. The previous article focused on methods related to the optimum use of memories; this one looks to exploit architectural features on the DSP itself.

Previous Features

News

Faraday Launches Configurable DSP Core
Following 8 months of redesign on the FD230 core, the biggest performance booster is the addition of a 2-way set associative instruction cache with a 4-instruction line size. This, hopes ASIC design-services firm Faraday Technology Corp., will lure customers targeting markets ranging from cable modems and DVD players to multichannel VoIP home gateways and GPRS smart phones.

Intel Poised to Roll Cellular Baseband With Flash
Manitoba, an integrated cellular baseband chip, is also known as Wireless-Internet-on-a-chip. The device includes a 400 MHz DSP, a 400 MHz XScale application processor, and as much as 16M bytes of the firm's Strataflash. Intel sandwiches these two cores along with its NOR flash in a 130 nm device.

Chip Heavyweights Compete to Kick-Start Mobile Data Apps
TI and STMicroelectronics are announcing ARM 926TEJ-based applications processors in competing bids to ignite the markets for mobile data processing and multimedia. Get a close look at how their offerings differ.

Configurable Core Boasts Compact Size, Novel Adaptive Data Path
Cambridge Consultants Ltd. has launched a DSP core that establishes a new price/performance benchmark for low-end SoC/ASIC applications. Despite the APE2's compact design—facilitating a 16-bit implementation using as few as 7000 gates—a novel adaptive-data-path architecture delivers impressive computational throughput. Processors can easily be configured to perform 10 parallel operations/cycle.

ChipWrights Intros Visual Signal Processor
The CW4511, the second ViSP family member, is built on a DSP architecture optimized for imaging algorithms. It's claimed to be the first programmable controller for both digital still and video camera applications that can operate at the speeds and power levels required to process full-motion video on a digital still-camera format.

Delphi and Philips Develop Software-Radio DSP
Philips' single-chip Car DSP, the SAF7730, enabled Delphi to develop proprietary radio software that will provide world-class reception performance through advanced DSP algorithms. This chip will become a key device in its future car-radio systems, says Delphi.

Adaptive Optics Give Terrestrial Telescope Steady Gaze
Astronomers at the University of Arizona are completing a ground-based telescope said to offer 3× better resolution than the Hubble Space Telescope. A main computer calculates mirror coefficients 550 times a second and passes them to a massively parallel computer with 168 DSPs. The heat generated from the DSPs and associated circuitry is removed with a cooling system that dissipates up to a kilowatt.

Are RISCs Putting CISCs Out of Business?
RISC processors are considered more modern, efficient, and cost-effective than older CISC chips. They're also generously endowed with better performance, lower power consumption, and higher speeds. So are CISC processors history? Not by a long shot, says Jim Turley, who claims that they actually dominate. Sometimes slow and steady really does win the race.

Genetic Algorithms Approximate Nonlinear Functions
Lookup tables and Taylor series are two common methods for interpolating between experimentally gathered data or for generating a known function such as a sine wave. This GA-generated integer-based function approximation is useful during prototyping as well as for direct implementation in a fixed-point processor.

Introduction to On-Chip Debug
Motorola's Background Debug Mode is one of a variety of on-chip debug technologies. Collectively, they offer some of the best features of debug monitors and in-circuit emulators, but with far less headache and cost. Further, an industry consortium called Nexus (aka IEEE-ISTO-5001) has established a standard for on-chip debug. If it's widely adopted, you might soon be able to use the same remote debugger to talk to processors from multiple vendors.

TI, Motorola, ADI Shine In '02 DSP Rankings
Texas Instruments dominated the DSP market in 2002, while Motorola surpassed Agere Systems as the world's second largest supplier of these chips, according to a report from Forward Concepts.

Former Broadcom, Altera Execs Form Processor Startup
Five experienced engineers and executives, including former Broadcom staff and the past managing director of Altera in Europe, have received $10 million for a startup. This fabless chip company, Icera Semiconductor Ltd., claims to have made a breakthrough in developing a new class of processor for wireless terminal devices.

Product Reviews

New DSP Simulation Technology from Texas Instruments Allows Designers to Model Full Applications in Minutes Instead of Hours
Jury Finds in Favor of National Instruments in Patent Infringement Lawsuit against The MathWorks
Motorola's Symphony Digital Audio Plays First Notes in a New Era of Digital Audio Technology
TI Introduces Industry's First 300 MHz Dual-MAC DSP at $5
Analog Devices Announces New High-Performance PCI-Based Emulator
An Engineering-Software Shootout
DSP Development Corp. Announces DADiSP/2002
Motorola Expanding 16-bit Hybrid MCU/DSP Portfolio
LSI Logic Introduces ZSP500—The Ultimate Open-Architecture DSP Engine for Multimedia and Communications Applications
Texas Instruments, The MathWorks® Collaborate on DSP Development Tools for Optimized Software Prototyping, Testing, and Verification
Texas Instruments Developer Conference 2002
DSP Group Unveils Next-Generation DSP Architecture Family—Scalable, Extendible, and Licensable
Improv Delivers Industry's First Low-Power, Multiple-Standard Media Processing Core
ADI's New Blackfin™ DSP—Part 4: Analysis of Dynamic Power Consumption
TI Introduces First DSP Emulator with Bidirectional Data Streaming at Video Speeds
ADI's New Blackfin™ DSP—Part 3: Powering Down

Product Reviews archives

Technical Features

Memory Techniques Lead the Way to Optimizing DSP Applications—Part 2: DSP Program Optimization
Memory Techniques Lead the Way to Optimizing DSP Applications—Part 1: Guidelines to Develop Applications
RTOS-Based Analysis Tools Simplify DSP-Application Debug and Optimization
Representation of Simple Sine Waves
New DSP design software uses a top-down methodology
Polyphase Resampling -- Part I
Frequency Shifting of a Complex Signal
Measuring Frequency and Phase of a Complex Signal
Fractional Resampling
Simple IIR Filters
An Intuitive Look at Matched Filtering - Part II
Technical Webcasts Offer Practical Solutions for Speeding Products to Market
The Costas Loop - Wrapping It Up
An Intuitive Look at Matched Filtering - Part I

Technical Features archives

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