Modern 0.18-micron technologies routinely allow integration of more than 10 million transistors on a single chip. As a result, a project team is expected to design a system on an IC that has more components than a Boeing 747. This overwhelming complexity is tamed by performing the bulk of the design at a high level of abstraction, the register transfer level (RTL). Converting an RTL description into a circuit is the job of Electronic Design Automation (EDA) tools such as logic synthesis and placement and routing software. Ideally, implementation should be a "push-button" action, but the combination of aggressive timing, advancing technologies and aging design flows have made this a labor-intensive and unpredictable process.

The continuing reduction of feature sizes poses an ever-increasing problem for traditional EDA systems that may have been developed 10 to 15 years ago for process technologies with much larger feature sizes. These systems were architected to address area constraints and optimize for gate delay. In today’s deep submicron (DSM) designs, area and gate delay are not the primary problems. The toughest problem is wire interconnect delay, which can represent as much as 80 percent of the entire chip delay.

Today’s Methodology

Interconnect delay is dependent on cell size and wire length and width. In a typical flow today, cell size is determined during synthesis and location of the cells and the wire routing is determined during place and route. The actual timing is not known until final layout extraction and timing analysis has been completed. Most often, the timing goal is not met. The timing information is then fed back to the synthesis tool in an attempt to produce a new netlist that has a better chance of meeting timing during place and route. So, in effect, today’s design tools incorporate effects of interconnect delay as an afterthought. And, instead of having a "correct by construction" flow, designers have to "construct by correction" through numerous iterations to resolve interconnect timing issues.

The decoupling of synthesis from place and route tools, or logic from physical design, is the root of the timing convergence problem. Synthesis can accurately model gate delay, but is forced to make crude approximations of interconnect delay because the real wire does not yet exist.

The approximations that synthesis makes are based on statistical wire load models. These models are little better than random numbers since actual wire lengths cannot be known until physical layout is complete. Real wire load and delay can differ dramatically from the statistically models. Logic synthesis makes decisions about the size of the cells or cell drive strengths before the actual wire loading is known. Since these decisions are made on questionable statistical data, iteration in the physical design space is unavoidable.

Postponing the sizing decision until parasitic wire loads are known solves the problem, and requires integration of logical and physical design.

FixedTiming Methdology: Controlling Timing with Logical Effort

Magma Design Automation’s patent-pending FixedTiming methodology provides a "correct by construction" flow for DSM designs. It establishes timing as the primary constraint and performs logic and physical optimizations to reliably achieve timing closure without iterations back through synthesis.

The FixedTiming methodology applies the theory of Logical Effort¹ to timing management. By using this theory, the delay of a gate can be reformulated as:

where g is the "logical effort," h is the "electrical effort," and p is the basic parasitic delay.

The logical effort formula captures the delay based on the logical complexity of a gate: The more complex the gate, the greater the delay. The "electrical effort" h is the gain of the gate, which is the ratio of the output and the input capacitances. Delay is held constant by changing the relative ratio of Cout to Cin.

Based on this formula, a limited ratio of capacitances can be chosen at the beginning and then held constant by re-sizing cells throughout physical design. This enables accurate control of delay by extracting the actual wire load parasitics instead of guessing what those parasitics might be based on a statistical model.

Figure 1 below shows how actual wireloads derived from initial placement and global routing can be used to optimize gate sizes and meet critical timing.

Figure 1 (a) illustrates initial balanced wireload estimates, (b) depicts increased cell size to maintain constant delay as wireload increases, (c) and (d) show how cell size adjustment ripples through all stages of a critical path.

Implementing FixedTiming Methodology

Magma’s Blast Fusion physical design system combines logic optimization and physical design into a single integrated flow. Blast Fusion accepts a synthesis netlist, but discards cell sizing information. Utilizing algorithms based on the FixedTiming methodology, Blast Fusion assigns an optimal delay to each cell, determines the best possible timing for the design, then concurrently places, routes and sizes each cell in order to meet that timing.

Reversing the conventional order of gate sizing and delay determination has additional advantages. Scaling and re-optimizing every cell to ensure proper drive strength for the parasitic wire load results in an electrically well-tuned circuit with the smallest size and lowest power consumption.

In addition, because Blast Fusion performs logic optimization and determines the best possible timing prior to layout, designers know early on whether or not it is possible to meet their timing goal with the given netlist. If the timing cannot be met, the designer knows that iterations back through synthesis cannot solve the problem. They know they must re-evaluate and change their architecture at the RTL level.

For more information on Magma or Blast Fusion, contact:

Monica Lawrence
Marketing Communications Manager
Phone: 408-864-2027
e-mail: monical@magma-da.com
or visit the company website at www.magma-da.com