The latest generation of deep submicron (DSM) processes, while boosting gate counts and enabling system on chip (SOC) design, has created a productivity gap and with it, technical and managerial challenges. In short, how do you cope with shrinking time-to-market and rising design complexity?

Designing a large system-level integrated circuit (IC) takes more effort than designing the individual components that made up the original chipset or printed circuit board. At the same time, each new generation of process technology brings shorter product life cycles, which demands shorter design cycles —— as little as 18 months for 0.25-µ processes. In some cases. DSM effects are making the final mask design stage more critical and time consuming because of increased parasitic effects that influence functionality and timing.

As a result of these difficulties, finding a more efficient design methodology is essential. Reusing hard intellectual property (IP) —— designs represented as mask layouts – by migrating it to more competitive processes is viewed as a way to overcome these design challenges.

Defining Hard IP

Hard IP has already been verified in silicon and is available as a physical layout in GDSII format. Functionality and timing are known and are based on a particular process technology.

Hard IP reuse can shorten the development cycle for new products. It reduces time-to-market for new products and accelerates the use of new manufacturing technologies. For DSM foundries, a good hard IP reuse methodology is essential to quickly re-create new cell-libraries and generators as design rules mature.

Reusing hard IP also carries with it some drawbacks that prevent it from becoming the universal solution for all reuse problems. One is the lack of flexibility. When functional changes are required in the design, hard IP reuse is not an option. For a successful SOC design, it will not be possible to continuously modify internals of existing designs —— a more rigorous and disciplined design methodology is required.

Reusing Hard IP

Here is a review of several popular methodologies:

Optical Shrink

Although simple to implement, an optical shrink produces an efficient design only if two processes were originally designed to allow efficient shrinking. This has been the trend for many submicron and older process generations, where rules of any new process could be tweaked enough to allow for efficient design shrink. With today’s DSM technologies, designing processes to allow efficient shrinks is impractical.

Common Design Rules

The idea of using worst-case design rule values for a number of comparable processes has been applied in previous process generations. Currently, the trend is toward diversity of rules, rather than common values. For the latest process generations, foundries are competing at the edges of technology that are difficult to unify into a common set of rules.

Symbolic Layout and Compaction

Rather than a hard IP reuse methodology, this is a design style for generating design rule correct hard IP layout. It is useful for hard IP reuse only if the original design was done in symbolic form. The bulk of existing designs do not benefit from this methodology.

Layout Migration

An example of layout migration is Design Rule Enforcement and Migration (DREAM), from Sagantec (See Figure 1). DREAM can be customized to fit the needs of a wide range of circuits for migration. Designers can migrate an existing cell library to meet new cell height requirements, new router gridding requirements and new transistor sizes. Regular structures —— RAMs and ROMs, for example —— are designed hierarchically and migrated hierarchically, exploiting the inherent regularity of the design to significantly reduce the necessary CPU time.

The term layout migration is used for a polygon compactor enhanced with utilities for preserving electrical characteristics. One of these utilities is a device-sizing tool, which determines length and width of each transistor in the target process, based on original dimensions and resizing rules provided by the user.

DREAM can automatically partition large, random logic, IP blocks into sub-blocks and migrate them separately, possibly distributed over a network of workstations.

Conclusions

Reusing hard IP by migrating it to next-generation processes allows it to be reused more reliably, requiring less effort for the creation of the final mask layout. By maximizing the amount of IP that reappears in the next-generation product, design teams can design next-generation products more efficiently and get them to market more quickly.

For more information on Sagantec or DREAM, visit the company website at www.sagantec.com or contact Nanette Collins at (617) 437-1822 or nanette@nvc.com

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