With the improvement in silicon manufacturing technologies, System-On-Chip (SOC) designs are now a reality. Although the SOC opportunities are clear, some significant, unresolved issues accompany them. Finding and implementing the right methodology to leverage these devices is arguably the most limiting problem confronting design companies today.

The weakest link in the SOC chain is the functional design and verification of the complete system. In an effort to solve this issue, disparate tools and techniques have emerged, resulting in a confusing and problematic design flow. The ultimate success of SOC depends on the development of a new, powerful design methodology.

The System-On-Chip Challenge

The key SOC methodology issue, enabling the design and verification of multi-million gate devices in a reasonable length of time, can be decomposed into the following requirements:

• Concurrent hardware/software implementation throughout the design process
• Efficient specification and creation of meaningful tests throughout the flow
• Ensuring the effectiveness and correct implementation of system algorithms
• The ability to track and debug complex, corner case style issues
• The utilization of various design blocks produced by separate design teams
• The combination of diverse hardware, software and system structures
• Unambiguous communication between different parts of the design team

A plethora of new design language proposals have been put forward to target the SOC problem. Although activity in this area is long overdue, tailoring existing programming languages created to meet differing needs, is fraught with issues that may not be apparent until the language is applied in real design scenarios.

So what are the essential ingredients in a design language recipe to meet the SOC challenges? A new language must Unify the complete SOC design flow, Speed up the design process, and allow Evolution from older methodologies — the so-called "USE-ability" requirements.

Meeting the USEability Requirements

The first requirement must be design flow unification. A new language must encapsulate the entire SOC design flow, including architectural specification, system partitioning and performance analysis, hardware implementation, software design, and functional verification. Such a language will break down unproductive walls between team members, eliminate inefficient interface bottlenecks, and make the flow faster and easier to learn.

The second requirement is a dramatic improvement in design speed. Language constructs to efficiently model complex system structures, make efficient use of existing and new tools, and enable fast coding and debug are essential. Designers must be able to use the language quickly, efficiently, and accurately.

The third requirement is the enabling of an evolutionary path from existing methodologies. A system is required that will allow design teams to use their current modeling styles and techniques and, over time, bring in new constructs, as required. With modern chip density expansion and third-party intellectual property production, design re-use has never been more crucial. By basing the language on an existing standard current models and techniques do not need to be replaced.

C / C++ -- Is This The Right Way?

Can C be used for systems design? Although C has its place in the SOC flow, particularly in the design of software, the programming language lacks timing and concurrency controls, and also is deficient in terms of advanced features required to model system structures. It has been suggested that a C++ class library be used to deal with some of these issues. Comparing this approach with the basic language requirements above yields interesting results.

Can C++ unify the design flow? Although C++ may be used for software design, the lack of powerful timing makes its use complex at best for describing protocols, dataflow, and other high level structures. Hardware description is tortuous with the C constructs getting in the way. This leads to the use of additional languages, such as an HDL, detracting from the unification aim.

Pure C can execute quickly in most parts of the design flow, but a scheduling class library results in reduced verification speed. Code to mimic system structures is relatively hard to write and complex to debug. Checking levels of abstraction against each other is complex and error prone.

Evolving to C from an HDL, such as Verilog, also has its drawbacks. Old Verilog code cannot be utilized in the new environment. C structures do not look like Verilog and a number of "hacks" must be inserted to make it behave the same way. Applying C to synthesis requires a whole new learning curve.

Utilizing the Best of All Alternatives

So, what’s the answer? It has been proposed that a language is required, designed to meet the SOC requirements of unification: speed and evolution. It is these requirements that have driven the new system design language, Superlog. Built using Verilog as a base, Superlog contains relevant C structures and special systems constructs to target architectural, software/hardware, functional test, and implementation. It works with existing tools as well as with new techniques such as high level synthesis and model checking.

SOC design requires new thinking if the creation of large, complex devices is to be accomplished. It is essential that a new design language is USEable, providing methodology unification, design cycle speed, and use model evolution if project teams are to get the most out of the available silicon area. Adapting languages developed for other purposes appears attractive and easy, but cannot deliver capabilities required for successful design flows. We need to architect a language to target the problem in hand, not hack an existing language to half satisfy some of the needs.

For more information, contact Co-Design Automation at info@co-design.com or write to Nanette Collins at nanette@nvc.com.

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