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* NEW * CynApps claims speed gains in C++ library By Richard Goering (11/29/99)
CynApps is claiming a sixfold performance boost in a new version of CynLib, its open-source C++ class library for hardware design, but the company's claim is based on a benchmark exercise whose originator says is not meant to be a meaningful comparison.. (EE Times)
High-Level Design Opens Up By John Sanguinetti (11/22/99)
Hardware design is becoming indistinguishable from software design, necessitating a rapid shift to hardware modeling using C++. (Electronic News)
Superlog language gains a dozen backers by Peter Clarke (11/22/99)
Designed from the ground up as a new high-level design language, Superlog provides an alternative to the recent C/C++ language proposals from the likes of Synopsys, CoWare and CynApps. (EE Times)
Verilog in a Tuxedo? by Stanley J. Krolikoski (11/22/99)
In a flurry of activity in system-level language development, the common thread among the various contenders is the search for a high-level language that captures designs at the system (pre-implementation) level. (Electronic News)
Synopsys unifies synthesis and placement by Richard Goering (11/12/99)
Promising a dramatic shift in the way high-performance chips are designed, Synopsys Inc. rolled out Physical Compiler, a single product that tightly couples synthesis with placement. (EE Times)
EDA startup spins C-based HDL by Richard Goering (11/10/99)
In an attempt to make hardware design easier for communications engineers, EDA startup EtherDesign Software is releasing a C-based hardware description language called C2HDL. (EE Times)
Cadence donates LEF, but spec's future still uncertain by Richard Goering (11/10/99)
Trying to put a divisive standards issue to rest, Cadence Design Systems released its Library Exchange Format (LEF) text specification to the Silicon Integration Initiative (Si2) in cooperation with the ASIC Council. (EE Times)
Cadence goes indirect on design services by Richard Goering (11/9/99)
Cadence Design Systems is rolling out a fresh approach to marketing design services by opening an indirect channel through Veba Electronics. (EE Times)
IP99: Designers see little need to move away from HDLs by Peter Clarke (11/5/99)
Hardware engineers are happy with VHDL and Verilog and are not eager to move away from hardware description languages to new higher level languages, according to a straw poll taken at a panel session at the IP99 Europe conference. (EE Times)
Model Technology revs Linux-based simulators By Richard Goering (11/4/99)
Marking a significant win for Linux-based EDA, Model Technology Inc. is making available its ModelSim EE and SE VHDL, Verilog and dual-language simulators for Linux platforms. (EE Times)
Assessing the Plethora of New Design Languages by Steven E. Schulz (11/4/99)
In the last six months, a remarkable number of new design languages and design language proposals have been introduced into the electronics industry. (Electronic News)
Is Your Design Team Talking? (10/31/99)
Dave Kelf, Co-Design Automationýs vice president of marketing, suggests that facilitating interaction between previously disparate design teams has become a paramount requirement for any new design language. ý (Dave Kelf, Co-Design Automation)
Symbolic simulation saves cycles (10/28/99)
The new Embedded Symbolic Processor (ESP) tools from InnoLogic use symbolic-simulation techniques to reduce the number of functional-simulation vectors you need to check a design (EDN)
Selecting A Code Coverage Tool by Michael Y.T. McNamara (10/17/99)
As engineers face what is being called a verification 'crisis,' they need an efficient way to measure how much of a design has been exercised during simulation. Michael (Mac) McNamara, president of Surefire Verification, offers tips on how to select a code coverage tool. (Michael McNamara, Surefire Verification)
System-level design languages: to C or not to C? by Graham Prophet (10/15/99)
If you have only recently begun to fully exploit HDL-based design with VHDL or Verilog, it will soon be time to move on and move up to a higher level of abstraction. But the languages may not be entirely new--they might even be very familiar. (EDN)
Design-team reuse by Graham Prophet (10/15/99)
This story considers some of the contenders vying to be the 'standard' language for system-level modelling in the system-on-chip era. (EDN)
Joint industry proposal for C-based system-design language (10/15/99)
To create a de facto standard, a group of companies from the EDA, intellectual-property (IP), systems, and semiconductor industries have collaborated to create the Open SystemC Initiative. (EDN)
InnoLogic launches symbolic simulation tools by Richard Goering (10/5/99)
Promising new technology that can solve some of today's toughest functional-verification problems, startup InnoLogic Systems Inc. is announcing two 'symbolic-simulation' products, which promise huge gains in functional coverage within existing design environments, (EE Times)
A la carte licensing: Will Avant!'s session-based licensing shake up the EDA world? (10/4/99)
Suddenly it's fashionable to sell software by the session. The idea is customers can use a program once and then buy another session, at another time, when they need it again. (Electronic Business)
The Need for New Design Languages (10/3/99)
It's a bird, it's a plane....it's Superlog. Simon Davidmann, CEO of Co-Design Automation, discusses the need for a new language to meet SOC requirements for design unification, speed, and evolution from existing methodologies. ý (Simon Davidmann, Co-Design Automation)
Synopsys and CoWare to embark on Open SystemC Initiative by Gale Morrison (9/29/99)
The scope of and venue for the next-generation design debate will change significantly as Synopsys Inc. and CoWare Inc. unveil their initiative for a common C++ system modeling platform. (Electronic News)
CynApps leads charge into C++ hardware design by Richard Goering (9/21/99)
CynApps's tool suite allows hardware design in C++, achieving what the startup company calls a breakthrough in high-level design. At its core is a C++-to-Verilog translator that works with CynLib, the C++ class library that CynApps recently made available from the company's Web site under an open-source license. (EE Times)
Managing Power in System-on-Chip Design (9/19/99)
Sente's Jerry Frenkil makes the case for resolving power issues at the architectural and register-transfer levels. (Jerry Frenkil, Sente)
Free tool shows simulation growth path to Xilinx customers By Michael Santarini (EE Times) (9/16/99)
Model Technology Inc. isl releasing two new versions of its ModelSim simulator to Xilinx Inc. customers to encourage them to adopt HDL-based design methodologies and possibly lead them to purchase larger Xilinx programmable logic devices. (EE Times)
Co-Design pulls Superlog from OVI consideration By Peter Clarke and Richard Goering (EE Times) (9/15/99)
Co-Design Automation Inc. has withdrawn its Superlog high-level design language from consideration by the architectural language technical subcommittee of Open Verilog International (OVI). (EE Times)
Reusing Legacy Data (9/12/99)
Sagantec product architect Chris W. H. Strolenberg looks at reuse and optimization of hard IP to meet the challenges of SOC design. (Chris W. H. Strolenberg, Sagantec)
Timing is Everything--The Case for Fixed Timing Methodology (9/5/99)
Patrick Groeneveld, principal engineer at Magma Design Automation, discusses a new approach to solving interconnect timing problems--a major cause of costly multiple iterations between front-end synthesis and place-and-route. (Patrick Groeneveld, Magma Design Automation)
Synopsys offers 'term-value' tool licenses By Richard Goering (EE Times) (9/1/99)
Synopsys Inc. is rolling out one-, three- and five-year ýterm value licenses and insists that it is taking a an approach that won't artificially inflate revenues. (EE Times)
EDA startups scramble for success By Richard Goering EE Times (8/26/99)
A look back at 1998 startups in EDA shows that most are still alive and shipping products, yet small EDA startups are facing an increasingly rocky road as venture capital (VC) money becomes harder to get, and more revenues fall into the hands of a few industry leaders. (EE Times)
Viewlogic adds interactive EDA support on Web By Richard Goering EE Times (8/24/99)
Moving to make better use of the World Wide Web for EDA product support and training, Viewlogic Systems Inc. this week has rolled out three new Web pages. The sites offer interactive training and instruction, a defect-tracking system and a visual diagnostic capability. (EE Times)
Ex-Summit CEO uncorks an e-commerce opportunity By Michael Santarini EE Times (8/23/99)
Ten months ago, Larry Gerhard was sitting atop Summit Design Inc., waiting to complete a merger with fellow EDA company OrCAD Inc. (EE Times)
EDA industry saw continued strong growth in first quarter By Michael Santarini EE Times (8/16/99)
The electronic design automation industry extended its streak of double-digit growth in the first quarter, according to the latest report from EDA Consortium's Market Statistics Service (MSS). (EE Times)
DAC Report (7/6/99)
Murray Slovick reports on the recent Design Automation Conference, where issues included use of the Internet to facilitate distributed design efforts, time-to-market pressures, and verification and intellectual property (IP). (ChipCenter)
Japan consortium looks to build IP distribution network By Anthony Cataldo EE Times (7/1/99)
Led by Fujitsu Ltd., the IP Highway Consortium will define a protocol for exchanging IP over the Internet, including catalog information, encryption, trace mechanisms, as well as design information such as RTL and gate-level simulation modeling. (EE Times)
Synopsys CEO calls for electronics renaissance By Michael Santarini EE Times (6/25/99)
Just like in the 1550s, when many factors converged on ship building to create a 'system-on-a-ship' which enabled global exploration, so too must design innovations converge to make system-on-a-chip define the renaissance of electronics. (EE Times)
Web-based tools gathering momentum By Craig Matsumoto EE Times (6/25/99)
Lucent Microelectronics said it plans to offer Web-based design software, with a project in the works to let users of Orca FPGAs configure their parts using software housed on a third-party server farm, and Cadence Design Systems tipped word of a beta program for Web-based verification. (EE Times)
Panel airs deep submicron design woes By Richard Goering EE Times (6/25/99)
While deep submicron design requires a closer link with silicon, it also requires higher levels of abstraction, noted participants at a recent DAC panel. (EE Times)
Rosetta language bows for system-on-chip designs By Richard Goering EE Times (6/21/99)
Rosetta and other proposed system-level languages promise to let designers work at much higher levels of abstraction than today's hardware-description languages. (EE Times)
EDA vendors redraw chip-design process By Richard Goering EE Times (6/15/99)
Everything you think you know about chip design will come under question at the Design Automation Conference (DAC) in New Orleans. (EE Times)
Avant! aims high with Jupiter front end By Richard Goering EE Times (6/14/99)
With its Jupiter 'design creation' software, Avant! Corp. is offering its first front-end design system complete enough to directly challenge Synopsys Inc.'s Design Compiler. (EE Times)
ICL Supervise simulator goes multilingual By Peter Clarke EE Times (6/9/99)
The design-automation group at ICL has enhanced its Supervise simulation technology to include a broad multilanguage capability with the development of the SuperviseMX simulator. (EE Times)
Startup promises verification tools for hard IP By Richard Goering EE Times (6/3/99)
Promising to facilitate reuse of hard intellectual property (IP), startup Altius Solutions Inc. is announcing its mission as a provider of verification tools for use with layout migration. (EE Times)
Startup to field next-generation design language By Peter Clarke EE Times (6/2/99)
Launching what appears to be the strongest private attempt in years to create a new high-level design language, Co-Design Automation's Superlog language combines the best features of Verilog and C/C++ while allowing interfaces and translations to and from C/C++, Verilog and VHDL, the company said. (EE Times)
VeriBest widens OS support By Michael Santarini EE Times (5/25/99)
The pc-board and FPGA tool vendor is announcing its first Verilog simulator and plans to offer all its HDL-based tools on Unix platforms by year's end, with Linux support to follow. (EE Times)
Moscape spins deep-submicron analysis tool By Michael Santarini (5/25/99)
Moscape Inc. brings deep-submicron analysis further up in the IC design process with its first tool release, CircuitScope v2.0. The tool, targeting structured custom design, has been maturing in the design flow at companies like Lara Technology and ATI Research over the past year. (EE Times)
Cadence and Philips Semiconductors Expand Relationship (5/18/99)
An agreement between Cadence and Philips Semiconduyctors includes the Envisia Ambit synthesis tool, a signoff-quality, fast, full-chip timing engine that enables high-capacity and high-performance chip-level synthesis. (ChipCenter: WebScan)
Synopsys VCS Standardizes on VirSim Graphical Analysis Environment (5/3/99)
Summit's VirSim verification debug and analysis environment will be bundled with Synopsys' VCS and VCSi Verilog simulators. In addition, VirSim post-simulation analysis capabilities, previously available as an additional cost option, will be included as a standard feature for VCS and VCSi products. (ChipCenter: WebScan)


Synopsys and SGI Demonstrate Parallel Computing Solution Based on Linux at SC99 (11/15/99)
The companies will focus on performance tuning of Synopsys' verification tools, including the VCS(TM) Verilog simulator, and will encourage other electronic design automation (EDA) vendors to provide related tools on the Linux platform. (ChipCenter: WebScan)
Verisity's Specman Elite Adds Dual-Language Support for Cadence's Affirma NC Simulator (11/15/99)
Verisity's Specman Elite, the company's testbench automation product, supports the Cadence Affirma NC simulator for both VHDL and Verilog hardware description languages. (ChipCenter: WebScan)
Cadence Releases Complete Physical Library Format (11/9/99)
Cadence Design Systems and Silicon Integration Initiative is releasing the complete Cadence Library Exchange Format (LEF) ASCII text specification to Si2 in cooperation with the ASIC Council. This release also includes the Application Programming Interface (API) and source. (ChipCenter: WebScan)
Companies cooperate on C/C++ services By Peter Clarke (11/4/99)
C Level Design Inc. has teamed up with Easics NV to offer design services for work done in C/C++ under a program called C-Expressway. (EE Times)
Linux Platform Offers High-Performance, Cost-Effective Solution for Simulation Farms (11/1/99)
Model Technology Inc. is making ModelSim EE and SE available for the Linux operating system in VHDL, Verilog, and mixed HDL configurations. (ChipCenter: WebScan)
Cadence Library Vendor Program Addresses COT Design Methodology Needs (10/25/99)
The Alanza Library Vendor Program, formed by Cadence Design Systems, aims to forge a tighter working relationship between Cadence and commercial library vendors to benefit customers by delivering a cohesive COT design methodology. (ChipCenter: WebScan)
Cadence claims silver lining in third-quarter loss By Richard Goering (10/21/99)
A year-to-year revenue decline of 32 percent would not be good news at most companies, but at Cadence Design Systems, executives are claiming that the third quarter shows a turnaround is underway. (EE Times)
Formal verification vendor Verysys goes bankrupt By Michael Santarini (10/21/99)
Formal Verification start-up Verysys Design Automation Inc. has been forced into bankruptcy. (EE Times)
VeriBest trims staff in refocusing bid by Richard Goering (10/20/99)
Denying persistent rumors of massive layoffs, EDA provider VeriBest Inc. claims it has removed a small number of middle-management personnel in a bid to refocus the company. But VeriBest is still scrambling for the growth and productivity that has eluded it since it spun out from Intergraph Corp. in 1996. (EE Times)
Acquisition feeds Sapphire plan for virtual prototyping tool by Michael Santarini (10/20/99)
Sapphire Design Automation Inc. has announced the purchase of Posedge Inc., a two-person developer of fast synthesis technology, and said it will use the company's tool as the foundation of a new RTL virtual silicon prototyping system. (EE Times)
Medea resumes EDA road map discussions By Peter Clarke (10/19/99)
A plan to forge a European road map for EDA development divides the domain of design automation into 14 topics and includes forecasts for when complete solutions to these tasks could appear on a time scale that extends through 2004. (EE Times)
Banner Half for EDA by Gale Morrison (10/19/99)
New electronic design automation (EDA) market data draws a picture surprisingly different than industry perception. Semiconductor intellectual property (SIP) revenue is down, though SIP is all the buzz. (Electronic News)
Aldec's VHDL Simulator Certified to Support the Real 64/66 PCI core from Xilinx (10/17/99)
Aldec's Active-HDLTM has passed the self certification requirements to support the Xilinx 64 bit/66 MHz as well as 32 bit/33 MHz LogiCOREý PCI products. (EDAC News Server)
Mentor Strides SOC Development By Jerry Ascierto (10/6/99)
Mentor Graphics Corp. at the Embedded Systems Conference West rolled out the latest version of its Seamless Co-Verification Environment (CVE) (Electronic News)
Avanti licenses design constraints format from Synopsys By Michael Santarini (9/30/99)
In a move that promises to smooth interoperability between their respective tool suites, Avanti Corp. and Synopsys Inc. have announced that Avanti has licensed Synopsys Design Constraints (SDC), a combined timing, clocking, area, power and test format for describing deep-submicron design intent. (EE Times)
Players Collaborate On Open C++ Modeling Platform (9/27/99)
Leading EDA, IP, semiconductor, systems and embedded software companies announced the Open SystemC Initiative and immediate availability of a modeling platform for free Web download. (ChipCenter: WebScan)
Council gives voice to telecom giants on EDA front by Peter Clarke (9/27/99)
In an effort to have more say in the development of systems-level electronic design automation tools, Europe's major telecommunications companies are coming together to create a body called the Systems Design Industry Council. (EE Times)
Viewlogic, Summit Design to merge By Richard Goering (9/17/99)
The merger of Viewlogic Systems and Summit Design will create a company offering EDA tools from the board level to mixed-signal designs. (EE Times)
Avanti ruling reduces financial liability By Richard Goering (EE Times) (9/13/99)
Part of the legal and financial cloud hanging over Avanti Corp. has dissipated, due to a ruling that will reduce Cadence Design Systems Inc.'s ability to claim punitive damages from its rival. (EE Times)
Hackers expose NT-based EDA tools By Richard Goering (EE Times) (9/9/99)
Anonymous hackers are offering software over the Internet that can bypass the widely-used FlexLM licensing utility from Globetrotter Software Inc., thus essentially allowing free, illicit use of Windows NT-based EDA tools. But anyone who uses it is liable for up to $1 million in fines and 10 years in jail, according to a Globetrotter spokesman. (EE Times)
Cogency postpones delivery of self-timed logic tools By Peter Clarke EE Times (9/7/99)
Cogency Technology Inc., the commercial pioneer of asynchronous, or 'self-timed,' logic, has postponed its plans to deliver EDA tools based on the technology and closed its European operations. (EE Times)
Cadence Selects Synopsys' Manufacturing Test Solution in Design Services Engagements (9/1/99)
Cadence has purchased Synopsys' DC Expert Plus for 1-Pass test synthesis and TestGen for automatic test pattern generation (ATPG) for use in methodology and design service engagements. (ChipCenter: WebScan)
EDA Companies Partner to Launch Verification Seminars (9/1/99)
Next month a group of EDA companies plan to share the latest industry trends and solutions for verifying electronic designs with HDL-based design and verification engineers and their managers. Participating companies include Axis Systems, Chronology, Denali Software, Model Technology, Novas Software, Verplex Systems and platform supplier Sun Microsystems. (ChipCenter: WebScan)
Synopsys seeds tools at Indian universities By Kariyatil C Krishnadas EE Times (8/23/99)
In a move that could help establish its position in the burgeoning Indian market in the long term, Synopsys Inc. will provide a range of front-end EDA tools to as many as 19 technical universities in India at a token cost. (EE Times)
Protel, Cadence fight for shrink-wrap EDA market By Richard Goering EE Times (8/9/99)
Protel International believes it's headed for leadership of the 'shrink-wrapped' EDA market following Cadence Design Systems' purchase of OrCAD. But Cadence claims it will be an even more aggressive competitor than OrCAD in the low-end EDA arena. (EE Times)
Seamless Interface between Synplify and Visual HDL Will Improve FPGA Design Flow (8/6/99)
Synplicity and Summit Design have agreed to develop an interface to Synplicityýs Synplify FPGA synthesis tool for Summitýs Visual HDL design-entry tool. (ChipCenter: WebScan)
Java-Based High-End Design Methods Explored (7/27/99)
Helping chip designers work at a higher level of abstraction in a standard software environment while dramatically boosting productivity continues to be an elusive goal for many EDA companies. (Electronic Design)
System-Level Design Language Promises A Unified, Integrated Design Flow (7/27/99)
For the past few years, industry experts have bandied around the concept of a system-level design language (SLDL) that would allow designers to intergrate and work with various components of a design--hardware, software, SoC, embedded components, and intellectual property.. (Electronic Design)
OrCAD and Veba Partner to Offer Online Design Capability (6/7/99)
OrCAD intends to provide an online environment for the design and manufacture of electronic products. Key in its strategy: Business relationships with top distributors and electronics manufacturers, the first of which is VEBA Electronics group. (ChipCenter: WebScan)
OrCAD Targets Both Analog and Digital Systems Designers with New Millennia Suites (5/24/99)
The OrCAD Millenniaý Suite, featuring OrCAD Captureý, OrCAD Layoutý Engineer's Edition, and OrCAD Express, is aimed at digital systems designers; and the PSpice Millennia Suite, including OrCAD Capture, OrCAD Layout Engineer's Edition, and PSpice, is for analog systems designers. (ChipCenter: WebScan)
Protel move shakes up shrink-wrapped EDA arena By Richard Goering EE Times (5/21/99)
Protel International Pty. Ltd. seeks to become a major player in the PLD-oriented 'shrink-wrapped' EDA marketplace with its acquisition of VHDL simulation from Accolade Design Automation, but the jury is still out on whether Protel can compete with OrCAD Inc., the clear leader in this market, or fend off FPGA vendors offering free or low-cost tools. (EE Times)
Protel acquires Accolade Design By Michael Santarini EE Times (5/18/99)
Recent acquisitions provide Protel with VHDL-based system design and FPGA design technology and with products that will directly compete with FPGA tool suites from such vendors as OrCAD and Accel Technologies. (EE Times)
Marconi Avionics Standardizes on Saber for Mixed-Signal/Mixed-Technology Simulation (5/13/99)
As part of a multi-million dollar, three-year partnership between the two companies, Marconi Avionics will standardize on Analogy, Inc.ýs Saber tool set for its mixed-signal and mixed-technology simulation requirements. (ChipCenter: WebScan)
HDL simulators roll for $99 By Richard Goering EE Times (5/13/99)
Attempting to bring highly capable yet low-cost EDA tools to first-time HDL users, Blue Pacific Computing Inc. is preparing to release $99 'student' versions of VHDL and Verilog simulators this year. The company will also offer free demo versions from its Web site, and field $499 'professional' versions toward the end of the year. (EE Times)
LavaLogic preps Java-based EDA tools By Richard Goering EE Times (5/12/99)
Claiming a 'revolutionary increase' in design productivity, EDA startup LavaLogic a business unit of satellite-data-processing vendor TSI TelSys Inc. is preparing to offer Java-based EDA tools. First out of the gate is a Java-to-Verilog RTL compiler planned for third-quarter release. (EE Times)
Synopsys VERA System Verifier Wins EDN Innovation of the Year (5/12/99)
The VERA System Verifier from Synopsys Inc., has won EDN Magazine's 1998 Innovation of the Year award in the EDA category. EDN Magazine's awards program honors outstanding engineering products in the electronics industry. (ChipCenter: WebScan)
Frontier to demo C-based architectural synthesis at DAC By Peter Clarke EE Times (5/11/99)
Frontier Design BV will demonstrate interactive architectural exploration and synthesis in the C language at this year's Design Automation Conference (DAC), which opens June 21 in New Orleans. The demonstration will feature a new type of EDA tool for those who want to do high-level hardware design in C prior to a conventional design flow based on Verilog or VHDL. (EE Times)
VSI, Synopsys split on verification spec By Richard Goering EE Times (5/11/99)
Taking sides in what has become a politicized standards dispute, the Virtual Socket Interface (VSI) alliance's Implementation/Verification 2.0 specification endorses two emerging standards instead of de-facto standards proposed by Synopsys Inc. (EE Times)
Numerical offers phase-shifting for deep-submicron ICs By Richard Goering EE Times (5/4/99)
Claiming to offer the first design tool that automatically phase-shifts deep-submicron IC designs, Numerical Technologies Inc. (NumeriTech) is launching its in-Phase product line along with foundry endorsements. NumeriTech said phase shifting is essential to next-generation processes below 0.18 micron. (EE Times)
Atmel/Synplicity solution exploits Atmel Macro Generator capability (4/28/99)
Atmel Corporation and Synplicity, Inc. announced support between Atmel's AT40K FPGA version 6.0 development software and the popular Synplicity Synplifyý logic synthesis tool (ChipCenter: WebScan)
EDA Industry Reports Record Revenue of $3.2 Billion for 1998 (4/23/99)
The EDA industry reported $3.263 billion ($US) in revenue for 1998, and grew by 24 percent in the fourth quarter of of 1998 (compared with the same period in 1997) to reach $908 million. (NASA Tech Briefs)
Dataquest Reports Viewlogic Leads Ready-to-Use Design Automation Software Market (4/20/99)
'The Shrink-Wrapped and Ready-to-Use Tool Markets' report from Dataquest Incorporated, a market research firm based in San Jose, Calif., notes that Viewlogic Systems, Inc., here, holds the leadership position in the ready-to-use Electronic Design Automation (EDA) software market. (ChipCenter: WebScan)


* NEW * New version of CynLib now includes support for NT and HP-UX (12/1/99)
Version 1.1 of CynApps's Cynlib, a open-source C++ hardware design library and simulator, has a new threads implementation that increases simulation performance. (Electronic News)
* NEW * Summit Design Launches Sixth Generation of Visual HDL (11/30/99)
Summit Design's Visual HDL is now equipped with a new Waveform editor that allows the graphical definition of test vectors and cycle-based patterns for functional block verification. (ChipCenter: ASIC)
* NEW * Verisity's Specman Elite Adds Dual-Language Support for Cadence's Affirma NC Simulator (11/30/99)
Specman Elite, Verisity's testbench automation product, supports the Cadence Affirma NC simulator for both VHDL and Verilog hardware description languages (ChipCenter: ASIC)
* NEW * Waveform Editor and Smart Compare Set Industry Standard for HDL Simulation Results (11/29/99)
Aldec, Inc., a leading supplier of HDL design entry and verification software for programmable logic designs, announced today Speedway TM1.0, a new ultra fast Waveform Editor and Smart Compare, a new waveform comparison software for Active-HDL Version 3.6. (ChipCenter: WebScan)
Summit Design Launches Sixth Generation of Visual HDL (11/18/99)
Summit Design's Visual HDL is now equipped with a new Waveform editor which allows the graphical definition of test vectors and cycle-based patterns for functional block verification. (ChipCenter: WebScan)
Agilent Technologies Extends EDA Simulation Software Offerings (11/16/99)
Agilent Technologies' new release of its Advanced Design System (ADS) electronic design automation (EDA) software helps communication product designers achieve a higher level of productivity by offering innovations in the areas of design automation, design education and usability. (ChipCenter: WebScan)
Linux port by Gale Morrison (11/9/99)
Mentor Graphics Corp. subsidiary that works in HDL simulation, is porting its two highest end tools, ModelSim EE and SE for 64-bit computer architectures and the Linux operating system. (Electronic News)
New Active-HDL 3.6 Simulator Increases Speed by 300% (11/8/99)
The most significant enhancements to Aldec's new Active-HDL 3.6 Simulator include shorter compilation time and up to 300% faster VHDL RTL simulation. (ChipCenter: WebScan)
Model Technology Provides Industry's First 64-bit HDL Simulator (11/1/99)
Model Technology will enhance its two most powerful tools, ModelSim EE and SE, to support 64-bit computer architectures, to provide its customers with significantly improved simulation capacity critical for system-on-chip (SoC) design verification. (ChipCenter: WebScan)
Synopsys and ARM Team to Deliver Industry's First Mixed-Language Solution for Secure, Portable IP Models (11/1/99)
Synopsys and ARM will offer the industry's first mixed-language simulation model creation and distribution solution for complex system-on-chip (SoC) designs. (ChipCenter: WebScan)
Synplicity Leverages Synthesis Technology (10/17/99)
Targeting system-on-a-chip designers, Synplicity is leveraging the companyýs core synthesis and partitioning technologies to allow designers to create functional hardware prototypes directly from RTL code (EDAC News Server)
Rate ATE compatibility at chip simulation (9/29/99)
You have to simulate your HDL chip model anyway, so wouldn't it be nice to be able to verify your automatic-test-equipment (ATE) test suite at the same time? With Fluence's TDS_SimValidator, you can. (EDN)
Mentor Graphics Extends Calibre Manufacturability Solution with Five New Products (9/20/99)
Mentor Graphics has extened its Calibre family of products, offering next-generation deep submicron (DSM) verification and manufacturability (ChipCenter: WebScan)
ldec Offers over 20,000 Xilinx Foundation Series Users a Seamless Interface to VHDL Simulation (9/15/99)
Invoked from the Xilinx Foundation Series Project Manager, Aldec's Active-HDL VHDL simulator can be used as a supplement for the gate level Logic Simulator shipped with Xilinx Foundation Series 2.1i adding VHDL simulation to the existing design flow. (ChipCenter: WebScan)
Model Technology and Xilinx Partner to Deliver Free HDL Simulation to Xilinx Customers (9/13/99)
Model Technology and Xilinx will provide a custom Xilinx version of the popular ModelSim simulator. ModelSim Xilinx Edition Starter (ModelSim XE Starter) will be offered free of charge to all registered Xilinx customers with current maintenance contracts. (ChipCenter: WebScan)
Language startup takes open-source route By Richard Goering (EE Times) (8/31/99)
Promoting its Cynlib C++ class library as a standard, CynApps, a system-level design language startup founded by EDA veteran John Sanguinetti, is making the library freely available from a company Web site. (EE Times)
Aldec Releases Student Edition of Active-HDL (8/26/99)
A Student Edition of Aldec's Active-HDL 3.5 software retains much of the functionality of the commercial version at a greatly reduced cost. (ChipCenter: WebScan)
ACCEL EDA Version 15 (8/2/99)
ACCEL's EDA Version 15 provides users with new and enhanced features to reduce design time through increased user productivity. (ChipCenter: WebScan)
HDAC adds coverage analysis to Solidify By Richard Goering (7/20/99)
Startup HDAC Inc.is rolling out a static-coverage-analysis option for Solidify, a static register-transfer level (RTL) functional analysis tool unveiled earlier this year. The company is also offering a client/server option that allows remote processing over a distributed network. (EE Times)
HDL Simulation for Altera APEX Devices (7/12/99)
Aldec's Active-HDL version 3.5 offers a seamless interface and simulation support for the Altera APEX device family. (ChipCenter: WebScan)
Suite Expanded to Include Verilog (7/12/99)
The Actel DeskTOP integrated suite of design tools has been expanded to include Verilog design entry and simulation. (ChipCenter: WebScan)
A Vendor-Independent Web Site for VHDL-AMS (6/21/99)
VHDL-AMS.COM will serve as an information source for early adopters of VHDL-AMS, providing available models written in VHDL-AMS, information about software tools and links to other web sites with VHDL-AMS relevant information as well as a platform for announcing VHDL-AMS related events. (ChipCenter: WebScan)
Integrated Cycle-Based Verification Solution (6/21/99)
PowerSuite is a fully integrated cycle-based verification solution, combining emulation and simulation tools in an extensible, multiple-engine methodology. (ChipCenter: WebScan)
Genedax, Avant! cut new paths for Web-based EDA By Richard Goering EE Times (6/21/99)
While there's been much discussion about remotely accessing EDA tools over the Internet, new licensing approaches are needed to make that happen. (EE Times)
Avant! Launches E(DA)-Commerce for Nova-Verilint and Nova-VHDLlint Products (6/21/99)
Edamall.com, Avant!'s new web site, will allow online U.S. and Canadian customers to license and download popular Avant! front-end chip design tools, Nova-Verilint and Nova-VHDLlint. (ChipCenter: WebScan)
Novas upgrades Debussy debugging environment By Michael Santarini EE Times (6/18/99)
Novas Software Inc. will release an upgrade to its Debussy Verilog and VHDL debugging software and field a new module for the tool. (EE Times)
Cadence Delivers Windows NT Versions of Affirma HDL Simulators (6/14/99)
Cadence Design Systems will support the Windows NT operating system with its full family of Affirmaý hardware description language (HDL) simulators for verification of application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), boards, and systems. (ChipCenter: WebScan)
Three-Vendor, Integrated Software Extends Actel DeskTOP Tool Series (6/7/99)
Actel DeskTOP Open features an open synthesis environment for customers who already have their own synthesis tools. (ChipCenter: WebScan)
Analogy Booklet and CD provides engineers with Hands-on Experience with VHDL-AMS (6/3/99)
Analogy's TheHDL Apprentice Preview Edition consists of a CD and VHDL-AMS mixed-signal booklet whose aims is to help engineers learn Analogyýs TheHDL single kernel, multi-language, open simulation environment and the recently standardized analog, mixed-signal and mixed-technology language extensions to VHDL. (ChipCenter: WebScan)
Analogy Unveils VeriasHDL Multi-Language, Single Kernel Simulator and VHDL-AMS Compiler (6/3/99)
Analogy's VeriasHDL a multi-language, single kernel simulator has a compiler for VHDL-AMS, the recently approved analog, mixed-signal and mixed-technology extensions to VHDL (IEEE Standard 1076.1-1999).. (ChipCenter: WebScan)
Denali's Object-Oriented Memory Modeler Uses OMI to Link to Affirma Simulators (5/26/99)
Cadence abd Denali Software will integrate Denali's Memory Modeler and Graphical Memory Debugger with the Cadence Affirmaý family of hardware description language (HDL) logic simulators. This integration allows mutual customers to rapidly generate customized memory models increasing functional simulation performance of system-on-a-chip (SOC) designs. (ChipCenter: WebScan)
Vantis First-to-Market with Top-Down VHDL/Verilog Synthesis and Simulation Tool Suite (5/24/99)
Vantis's DesignDirect 'Vista' software is a hardware description language (HDL)-independent synthesis and simulation tool suite. The Vista package includes shrink-wrapped flows by Exemplar Logic's LeonardoSpectrum synthesis tool, and Model Technology's ModelSim simulator, and has new enhancements to the core software for high Quality of Results (QOR). (ChipCenter: WebScan)
Lattice Semiconductor Adds Fusion/SpeedWave-Lite VHDL Simulator (5/24/99)
This latest Lattice release supports VHDL design verification for Lattice's ispLSI devices up to 600 macrocells in density as a standard feature. (ChipCenter: WebScan)
Formal Verification Combination Delivers Cost-Effective Approach (5/20/99)
A Cadence Design Systems product bundle combines Envisia Ambit synthesis software with the Affirma equivalence checker software. (ChipCenter: WebScan)
Escalade Announces Design Extractor for Corporate Design Reuse (5/17/99)
Escalade Corporation's Design Extractor generates language-independent graphical models from legacy register transfer level (RTL) designs in Verilog and VHDL (ChipCenter: WebScan)
Aldecýs New HDL Editor Is Web Enabled (5/17/99)
The new HDL editor that is part of Aldec's Active-HDL design environment is web enabled, supports VHDL and Verilog design entry and is tightly integrated with Aldec's HDL simulator. (ChipCenter: WebScan)
Aldec Automates HDL Design Verification Techniques (5/3/99)
Among the enhancements to Aldec's Active-HDL environment are advanced Simulation Waveform Comparisons, automatic VHDL Testbench generation from graphical waveforms, and TCL/TK scripting that produces interfaces to third party logic synthesis and implementation tools. (ChipCenter: WebScan)
Tau Simulation upgrades cycle-based simulator By Michael Santarini EE Times (4/29/99)
Tau Simulation has introduced version 4.0 of its synchronous Verilog simulator, which offers greater flexibility than eariler versions in its support of sophisticated clocking domains and higher simulation speeds. (EE Times)

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