DATE Keynoter Lists Challenges to Tech Complexity
The algorithmic complexity of systems is bound to outpace Moore's Law, according to a keynote speaker at this week's Design Automation and Test in Europe conference. "This is going to force us all to think like systems companies," said Andrea Cuomo, corporate vice president and general manager of Advanced Systems Technology at STMicroelectronics (Agrate, Italy).

DATE Attendees Ponder 90nm Test Strategies
The Design Automation and Test in Europe (DATE) conference revealed a surprising profusion of advanced concepts in circuit and system design. Perhaps one lesson of the SoC era will be that nothing can exist as an isolated specialty. For example, an entire day at the conference is being set aside to explore the concept of Ambient Intelligence described by organizers to be "a new paradigm for user centered computing and interaction, combining aspects of ubiquitous computing, natural interaction, and intelligence."

Mentor, Magma ties raise eyebrows at DATE
Heavy joint marketing activity between Mentor Graphics Corp. and Magma Design Automation at the Design Automation and Test (DATE) conference in Munich this week got the attention of Jay Vleeschhouwer, analyst at Merrill Lynch, who commented on the cozy relationship in his Wednesday DATE report.

ST Proves Diagonal Interconnect, Plans Chips in 2004
STMicroelectronics has working silicon of the X Initiative's promised diagonal interconnect regime and is on course to make commercial chips based on diagonal wiring in 2004. Jean-Pierre, Schoellkopf, a senior expert in central R&D at STMicroelectronics discussed the success on an X Initiative sponsored panel at the DATE exhibition having recently produced the first test chips in 130-nanometer process technology.

Transaction-Based Methodology Supports HW/SW Co-Verification
Engineers are wondering how to leverage all of the point tools that have been developed to solve specific issues to create a single, cohesive methodology that some call "unified verification." This paper describes how engineers doing system-on-chip (SoC) verification can be more efficient by using a single, reconfigurable verification system, applications, and a unified methodology that allows engineers to execute hardware and software tests with a flexible mix of performance and debugging.

DVCon: SystemVerilog Key to New Design Paradigm
The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO Aart de Geus. The move is intended to solidify SystemVerilog as the next significant productivity booster for chip design, he said in a DVCon keynote speech, "Design For Verification: a new paradigm."

Verilog 2001 Compliance Lacking, Designer Says
Even as EDA vendors promise support for the upcoming SystemVerilog 3.1 standard, compliance with the earlier Verilog 2001 IEEE standard is spotty and inconsistent, according to a paper presented at the DVCon Design and Verification Conference.

Placement Tools Criticized for Hampering IC Designs
Current IC placement algorithms leave so much excess wire that chip designs are essentially several technology generations behind where they could be, according to a recent paper by researchers at the University of California at Los Angeles (UCLA). EDA vendors have responded by stating that commercial placement tools are not as deficient as the study suggests.

MEMS Tool Company Teams with Cadence
Coventor Inc., a North Carolina-based provider of design tools for micro-electrical mechanical systems (MEMS), has announced a partnership with leading EDA company Cadence Design Systems Inc. to build a comprehensive design suite for next-generation MEMS and microfluidic devices.

Work Group Forms to Link Two EDA Interfaces
A standard application programming interface for IC design data will come closer to reality this week, when the OpenAccess Coalition and Synopsys Inc. form a working group to link the OpenAccess and Synopsys Milkyway APIs. If successful, the effort will produce a single API that will provide far greater interoperability than EDA users have known.

EDA Veteran Launches Low-Power Design Services Firm
Design services have taken a beating in the ongoing electronics industry slowdown, but EDA veteran James Lee thinks he has an approach that will work - a small firm comprised of system-on-chip experts who focus on low-power, portable design. Lee launched his new company, The ASIC Group, late this year after his former employer, Intrinsix Corp., consolidated operations.

Mixed-Signal Design Flow Enables RF CMOS Chip
Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a design and verification flow, using off-the-shelf design tools, that enabled leading-edge CMOS design techniques for RF, mixed-signal and digital designs.

Magma joins Virage as Distributor of TSMC Cell Libraries
EDA tool vendor Magma Design Automation Inc. has joined Virage Logic Inc. as a distributor of libraries of standard cells and I/O cells from Taiwan Semiconductor Manufacturing Co. Ltd. Magma is able to offer TSMC's 130-nanometer and Nexsys 90-nm libraries to both companies' mutual customers, integrated with Magma's design automation software. The libraries are available at no charge but require a fee-based support contract from Magma.

Design Automation Conference Registration Opens
Registration is open for the 40th Design Automation Conference (DAC), to be held June 2-6, 2003, in Anaheim, California. DAC organizers decided to open registration earlier than usual and keep it open until late May.

Mentor Graphics Boosts India Investment
Mentor Graphics Corp. (Wilsonville, Ore.) plans to invest another $50 million in its Indian operations over the next five years. The company has two development centers in India, one at Noida near New Delhi, and another at Hyderabad in southern India. Mentor executives have said India would be a strategic research and development center for its global operations.

Get Rid of the Noise, Keynoter Advises
Signal integrity has become designers' No. 1 hurdle as chips, boards and systems approach transfer rates of 10 Gbits/second, keynoter Henri Merkelo told the PCB East conference. Designers have got to turn down that noise, and need algorithms that "simulate everything from circuits to connectors to solder bumps," said Merkelo, chief executive officer at Speed Technologies Corp. (Harrisburg, Pa.).

Mentor Provides Link to Arrow Component Database
Mentor Graphic Corp. will allow pc-board designers and layout engineers to add the Ubiquidata database of Arrow Electronics Inc. to its Data Management System (DMS) solution under an agreement between the companies. The database includes more than 16 million electronic components.

Cadence sues Mentor for Malicious Prosecution
Reacting to a flood of ongoing patent litigation lawsuits, Cadence Design Systems Inc. has filed a lawsuit charging Mentor Graphics Corp. and Aptix Corp. with unfair business practices. Cadence is seeking to recoup its costs from a 2000 lawsuit in which a judge accused Amr Mohsen, Aptix's chief executive officer, of massive fraud.

Solutions Proposed for Verification Crisis
A validation crisis is stalking system-on-chip designs, according to a panel session at the 15th IEEE International ASIC/SoC Conference, though panel participants cited two possible routes toward its resolution.

EDA Industry Records Dismal Second Quarter
Electronic design automation industry revenues were down 10 percent in the second quarter of 2002 compared to the previous year's quarter, marking the sharpest year-to-year drop in revenues since the EDA Consortium started tallying numbers in 1996.

Smart Verification Moves Beyond SystemVerilog 3.0
HDL simulation tools need to evolve to become a verification platform by making "smart verification" technologies, such as testbench features, assertion technologies, advanced coverage technologies, and C++ extension available within the simulator.

OpenAccess API Could Link Design, Manufacturing
A powerful coalition of chip makers, mask makers, equipment providers and EDA vendors will gather in Monterey, Calif. to call for a single design-through-manufacturing data model based on the OpenAccess application programming interface.

Cadence Buys IBM's Design-for-Test Tools Business
Bolstering its position as the EDA industry's leading supplier, Cadence Design Systems Inc. has purchased the design-for-test technology and group personnel of IBM Microelectronics for an undisclosed amount of cash. Cadence has also signed a technology development pact and a tools license with IBM.

Synopsys Adds Logic BIST Tool to Test Solutions
Synopsys is entering the logic built-in, self test (BIST) market this week with a tool named DFT Compiler SoCBIST, which will reduce both tester time and data volume, the company said.

Mentor Graphics Offers Speedy Support for GDSII Replacement
Mentor Graphics Corp. has said it will support a replacement data format for GDSII that it helped to develop in its Calibre product family and the IC Station tool suite in the first quarter of 2003

Synopsys snaps up Co-Design for Superlog language
EDA leader Synopsys Inc. has struck a deal to acquire privately held startup Co-Design Automation Inc. for approximately $36 million in cash and stock options.

EDA vendors ponder 90-nm tools

Cadence releases revised signal integrity tool

EDA startup develops new design language

Intel adopts strained silicon for 90-nanometer process
In a surprise move, Intel Corp. said that it will add strained silicon technology to its 90-nanometer technology mix, and will use the process to make the Pentium 4 microprocessor code-named "Prescott" starting next year.

Exploring new design flows -- integration and automation

Keynoter Says Chip Value is in its Intellectual Property
Silicon complexity and rapidly changing architectures are making embedded software development much more difficult, said Jerry Fiddler, founder and chairman of Wind River Systems Inc., in a keynote speech at the 39th Design Automation Conference.

Cadence, Synopsys Aim for Parallel Routing
Both Cadence Design Systems Inc. and Synopsys Inc. plan to offer parallel processing for chip routing at the 90-nanometer node. Representatives of both companies said at the Design Automation Conference that they are rolling out support into their place-and-route tools for techniques to split the intense routing workload across multiple processors and machines.

Diagonal Chip Wiring may be Routine by 2004
Diagonal wires may become routine by 2004, according to STMicroelectronics, one of the companies working to implement chips that use the 45-degree on-chip interconnect technique promoted by the X Initiative.

Verified Designs Cited as Industry Goal

Designers, Providers Weigh Value of Unified

Designers Report on Multi-Million Gate ASICs

DAC Technology Trends: Confronting Timing and Signal Integrity

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