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Design Automation -- EDA tools Subsections

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Features

- New - OpenAccess Releases Source-Code Roadmap
OpenAccess, based on the Genesis database developed by Cadence Design Systems, Inc., is the industry's first open, standard database. The database will enable the building of a truly interoperable infrastructure for electronic design technology. (ChipCenter: ASIC)

News

- New - ChipPAC Adopts Cadence IC Packaging Design Technology
ChipPAC, Inc., one of the world's largest and most diversified semiconductor packaging, test and distribution providers, has standardized on the Cadence(R) integrated circuit (IC) packaging design suites, Advanced Package Designer and Advanced Package Engineer, to further automate its IC packaging design process and reduce cycle times. (e-inSITE)
- New - Mentor Graphics Showcases New Mask Data Prep Technology
Mentor's new MDP software completes the layout-to-silicon flow, which will be formally introduced March 11. This extension of the Calibre physical verification and manufacturability tool suite enables semiconductor companies that have standardized on Calibre to export mask-ready data from Calibre directly to mask-writer formats such as MEBES. (ChipCenter: WebScan)
- New - Monterey Customer Milestones Drive Expansion In Europe
Monterey Design Systems has doubled the size of its European sales and support staff in response to growing customer demand for its System-Driven Physical Design� solution (SDPD). (ChipCenter: WebScan)
- New - Analog simulation tools look to better Spice
Nassda said HSIM 2.0, the latest version of its full-chip verification tool, identifies power leakage and other parasitic effects peculiar to nanometer-scale IC designs. Ansoft's version 4.0 of its Turbo Package Analyzer tool analyzes electromagnetic effects and other parasitics in complex semiconductor packages. (EE Times)
- New - Sequence leads initiative to create deep-submicron design flow
In an ambitious effort to create a design flow for low-power, low-voltage deep-submicron ICs, Sequence Design Inc. this week will launch its NanoCool initiative, under which Sequence and various partners will combine new and existing products and capabilities ranging from design planning through post-route verification. Sequence will also announce the first new tool created under the initiative: IP Wizard, which automates the creation of power models for silicon intellectual-property (IP) blocks. (EE Times)
- New - Toshiba America Electronic Components Achieves Placement Handoff With Synopsys Physical Compiler
Toshiba America Electronic Components Inc. has adopted Synopsys' Physical Compiler� for placement-based handoff. TAEC has already deployed the placement handoff flow with Physical Compiler to successfully tape out two complex system-on-chip (SoC) designs for a strategic customer. TAEC in now including Physical Compiler in its design flow as well as making the tool an integral part of the design kit for its ASIC customers. (ChipCenter: WebScan)
- New - Virtual Silicon eSi-Route Libraries Now Available For PrimeTime SI
Virtual Silicon eSi-Route� standard cell libraries are now available for PrimeTime� SI. These libraries-characterized with the Silicon Metrics SiliconSmart CR� tool and qualified to support the patented delay calculation capabilities in PrimeTime SI-target 0.18um and 0.13um designs in the fabless flow. With PrimeTime SI in the flow, customers are able to pinpoint crosstalk-induced timing problems quickly and reduce the risk of chip failure. (ChipCenter: WebScan)
- New - Mentor Introduces SpeedGate
SpeedGate DSV (Direct System Verification) is an advanced verification environment for creating application specific integrated circuits (ASIC) and System-on-a-Chip (SoC) prototypes using off-the-shelf field programmable gate arrays (FPGAs). Silicon prototypes created by SpeedGate DSV can be tested at speeds comparable to a real-time operating environment, significantly reducing costly, time-consuming silicon respins. (ChipCenter: ASIC)
- New - Qualis debuts reusable verification components
Qualis Design Corp.has launched its first standalone Domain Verification Components (DVCs), building blocks which support verification 'reuse' by providing protocol-specific test environments for Synopsys Inc.'s Vera and Verisity Design Inc.'s Specman products. (EE Times)
- New - Quickturn Palladium System Deployed By QLogic
QLogic Corporation's Network Storage Group has purchased the Quickturn Palladium(TM) design verification system. QLogic will use it as the platform for verifying its Fibre Channel switches, adapters, and switch management products. (ChipCenter: WebScan)
- New - The MathWorks Improves System-Level Design
The Developer's Kit for Texas Instruments DSP 1.2, allows systems and software engineers to develop and verify DSP algorithms in one integrated environment, thereby efficiently producing designs. The new version provides improved integration with eXpressDSP� software and development tools through its compatibility with Code Composer Studio� 2.0 and 2.1 and expanded code generation support for popular TI DSP devices. (ChipCenter: WebScan)
- New - Cadence And Agilent Technologies Strike Alliance
Through this alliance, the industry leaders in electronic and radio-frequency (RF) design respectively expect to develop and market complete integrated solutions to speed the design of ICs for the wireless and wireline communications industries. (ChipCenter: WebScan)
- New - Simplex Rolls SI Tools
SignalStorm SOC analyzes propagation delay, voltage drop (IR) and crosstalk effects via next-generation, hierarchical delay calculation. (Linux Net News {scan via})
- New - Agilent Technologies incorporates Agere Systems' software for RFIC design
Agilent will incorporate Agere's Schur Complement Preconditioner software for harmonic balance simulations into Agilent's Advanced Design System (ADS), a suite of EDA software tools for the design of products such as cellular and portable phones, pagers, wireless and broadband networks, and radar and satellite communications systems. (Test & Measurement World)
- New - Artisan Components Qualifies Libraries For PrimeTime SI
Artisan's SAGE-X� 0.18- and 0.13-micron family of standard cell libraries are now qualified and immediately available for Synopsys PrimeTime� SI. With PrimeTime SI and Artisan's SAGE-X libraries in their nanometer design flow, customers are able to pinpoint crosstalk-induced timing problems quickly, thereby reducing the risk of potential chip failures. (ChipCenter: WebScan)
- New - Altium announces new Design Capture
The new Design Capture product with the working name �nVisage� is to be included in the upcoming version of Altium's Protel board-level design system. nVisage is a versatile and fully integrated Design Capture system for professional engineers which integrates schematic design entry with schematic and text-based VHDL design, and allows a single design to be captured using any mix of these design entry methods. (ChipCenter: WebScan)
- New - Oki Semiconductor Standardizes on Mentor Graphics Calibre
Oki Semiconductor has standardized on Mentor's industry-leading Calibre� physical verification tool for designs in advanced process technologies of .35, .25, .22 and .16 micron. Oki chose Calibre because previous physical verification tools proved inadequate for the multi-million-gate integrated circuits that Oki designs and markets for telecommunications, network, automotive, computer, and consumer products. (ChipCenter: WebScan)
Synopsys and UMC Collaborate On Signal Integrity Test Chip
The chip, dubbed ATG-SI, contains test structures that allow the study of multiple threshold voltages, inductance effects and model extraction. The chip also tests other signal integrity issues, including crosstalk and noise, which affect the performance and reliability of today's aggressive system-on-chip (SoC) designs. (ChipCenter: WebScan)
DesignCon panel explores deep submicron challenges
Two user panelists and two EDA vendor panelists discussed the challenges of deep submicron, 50-million-transistor chips at DesignCon 2002. Issues such as tool capacity, signal integrity and the challenges of analog/mixed-signal circuitry emerged as consistent themes. (EE Times)

Resources

ChipCenter Reference Library
This is your access point for lots of good information covering applications, design tools, consultants, intellectual property, trade shows and standards.
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