FPGAs, Programmable Logic

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Design Automation -- FPGAs, Programmable Logic Subsections

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News

- New - Xilinx And Cast Announce Immediate Availability Of Digital Video Technology Cores
The new cores target a wide range of digital video applications, such as desktop video editing, digital still cameras, set-top boxes, and digital televisions. Immediately available from CAST, the new cores include image compression, wavelet-based image and video CODECs, and digital signal processing. (ChipCenter: WebScan)
- New - Xilinx And Cast Announce Immediate Availability Of Digital Video Technology Cores
Xilinx, Inc. and CAST, Inc.have announced the immediate availability of six new cores for Xilinx Virtex and Spartan FPGA families. The new cores target a wide range of digital video applications, such as desktop video editing, digital still cameras, set-top boxes, and digital televisions. Immediately available from CAST, the new cores include image compression, wavelet-based image and video CODECs, and digital signal processing. (ChipCenter: WebScan)
- New - Actel Updates Libero Integrated Design Environment
Actel Corporation has enhanced Libero, its next-generation integrated design environment. Libero now supports Actel's recently announced application-specific integrated circuit (ASIC) replacement solutions, the ProASICPLUS flash-based field- programmable gate array (FPGA) family. (ChipCenter: WebScan)
- New - Aptix Supports Xilinx Virtex-II
Aptix Corporation announced the availability of the Virtex-II Prototyping Module incorporating the XC2V6000 Virtex-II Platform FPGA from Xilinx. (ChipCenter: WebScan)
- New - Xilinx And Umc Announce Revolutionary Cpld Process Roadmap
Xilinx, Inc. and UMC today unveiled the industry�s first CPLD process technology scalable to 100 nanometer. (ChipCenter: WebScan)
- New - Velio And Xilinx Collaborate
Velio Communications, Inc. and Xilinx� Inc. have collaborated to successfully develop a platform to demonstrate hardware interoperability between Velio's SONET-EOS (Eye-Opening SerDes) family and Xilinx Virtex�-II Platform FPGAs. The evaluation platform can be used as a reference design to help accelerate the development of the emerging OC-192 communication systems. (ChipCenter: WebScan)
- New - Xilinx Delivers Its Largest-ever Performance Lead e
Benchmarks of customer and IP core designs show ISE 4.2i delivers 70 percent faster clock speeds on high-density next-generation Virtex�-II designs than the nearest competitive offering with available silicon. (ChipCenter: WebScan)
- New - Mentor Graphics Introduces Direct System Verification Environment for Rapid ASIC Prototyping
Silicon prototypes created by SpeedGate DSV can be tested at speeds comparable to a real-time operating environment, significantly reducing costly, time-consuming silicon respins. (ChipCenter: WebScan)
- New - Xilinx Expands Encryption/Decryption Solutions
Xilinx, Inc. has announced the availability of new Advanced Encryption Standard (AES) intellectual property cores and services to support the growing demand for encryption/decryption and security applications. (ChipCenter: PLD)
- New - Altera�s �Xilinx Killer� Stratix Debuts
Altera Corp. claims its new PLD architecture offers a 40 percent push-button performance increase over its previous APEX II devices. The company said its Stratix device family is built on a new routing architecture and has a die size 35 percent smaller than previous architectures. It has up to 10Mbits of RAM and up to 114,140 logic elements. (Electronic News)
- New - Atmel Intros Family of Secure/Programmable SoCs
Atmel's programmable SoC family reportedly eliminates the need for external memory to store the FPGA configuration data and processor program code by integrating the configuration EEPROM with the FPSLIC programmable SoC in a single 256-pin micro BGA package. (Electronic Business)
- New - Altera courts ASIC designers
The Stratix architecture aims to ratchet up logic density and speed while giving designers ways to take advantage of more modular, reusable intellectual-property blocks and tighter memory configurations. Stratix is being positioned as a worthy substitute for system-on-chip designs based on an ASIC methodology. In fact, Altera's engineers made heavy use of simulations based on existing ASIC designs as they developed Stratix. (EE Times)
- New - Altera looks to regain PLD crown
Eight months ago, when Altera Corp. pledged to get closer to its top customers, the seeds had already been planted for a development the company now claims will redefine the programmable logic landscape. The result is Stratix, a general-purpose PLD architecture. (Electronic Buyers' News)
Aldec to offer Synplicity's Synplify Pro� tool through University Program
Aldec, Inc. will be offering Synplicity's Synplify Pro product bundled with Aldec's Univeristy Program products to accredited universities for teaching and research purposes only. Aldec will provide Synplify Pro licenses (PC or UNIX floating) to universities and research institutions for a 1-year or 3-year period. (ChipCenter: WebScan)
NU Horizons Announces First Modular Development Solution For Design Engineers Featuring Xilinx FPGAs
Unlike traditional stand alone board solutions, the new Platform consists of a highly functional main board that has the ability to add up to two additional application specific development cards, providing design engineers with a modular hardware platform to develop, prototype, verify and test designs before they are finalized. (ChipCenter: WebScan)
Xilinx and Model technology Deliver Five Times The Improvement In Verification With Extended Oem Relationship
This agreement gives Xilinx customers a more powerful version of the popular ModelSim Xilinx Edition (MXE). MXE II, based on ModelSim 5.5e, delivers five times the verification capacity, which is equivalent of simulation for up to one million system-gate designs. (ChipCenter: WebScan)

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