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Design Tasks
Design Entry
Design Entry : Constraint/Data/Workflow Mgmt / Interoper
Design Entry : Hardware Description Language
Design Entry : Hardware Description Language : Other, C, C++
Design Entry : Hardware Description Language : Verilog
Design Entry : Hardware Description Language : Verilog-A
Design Entry : Hardware Description Language : Verilog-AMS
Design Entry : Hardware Description Language : VHDL
Design Entry : Language / Design Support
Design Entry : Language / Design Support : Access Functions
Design Entry : Language / Design Support : Analyze/Comp/Elab//Dbug/Edit
Design Entry : Language / Design Support : Browser
Design Entry : Language / Design Support : Code Coverage
Design Entry : Language / Design Support : Database Compression
Design Entry : Language / Design Support : IP Protection
Design Entry : Language / Design Support : Scripts
Design Entry : Language /Design Support : Rule / Style Checker
Design Entry : Libraries, Cores, Models, IP, Re-Use
Design Entry : RF / Microwave
Design Entry : Schematic/Graphical/FSM/Ttable
Design Entry : System Level / DSP
Functional Verification
Functional Verification : Accelerators & Emulators
Functional Verification : Formal Methods
Functional Verification : Formal Methods : Design Rules Checker
Functional Verification : Formal Methods : Equivalence Checker
Functional Verification : Formal Methods : Model Checker
Functional Verification : HW / SW Co-Design / Verification
Functional Verification : Other
Functional Verification : Simulators
Functional Verification : Simulators : Analog / Analysis & SPICE
Functional Verification : Simulators : Analog / Behavioral
Functional Verification : Simulators : Digital Simulation
Functional Verification : Simulators : Digital Simulation : Cycle-Based Simulation
Functional Verification : Simulators : Digital Simulation : Gate / Other
Functional Verification : Simulators : Digital Simulation : Language Co-Simulation
Functional Verification : Simulators : Digital Simulation : Verilog Simulation
Functional Verification : Simulators : Digital Simulation : VHDL Simulation
Functional Verification : Simulators : Mixed-Signal
Functional Verification : Simulators : Other
Functional Verification : Simulators : RF / Microwave
Miscellaneous
Miscellaneous : Design for Manufacturing (DFM)
Miscellaneous : Embedded Systems
Miscellaneous : Embedded Systems : Compile/Assemble/Link/Debug
Miscellaneous : Embedded Systems : HW / SW Virtual Prototype
Miscellaneous : Embedded Systems : Other
Miscellaneous : Embedded Systems : Real-Time Operating Systems
Miscellaneous : Mechanical Design & Packaging
Miscellaneous : Reliability
Miscellaneous : Translation Tools
Miscellaneous : Translation Tools : Database Translator
Miscellaneous : Translation Tools : Language Translator
Miscellaneous : Translation Tools : Netlist Trans / Generator
Miscellaneous : Translation Tools : Schematic Translator
Miscellaneous : Translation Tools : Verilog-VITAL Translator
Miscellaneous : Waveform Viewing
Miscellaneous : Wiring Harness Design
Physical Design
Physical Design : Cell / Device Model / Characterize
Physical Design : Custom / Automated Mask Layout
Physical Design : Design Migration
Physical Design : Floorplanning / Partitioning
Physical Design : Layout Compaction
Physical Design : Logic Optimization
Physical Design : Photomask Synthesis
Physical Design : Placement / Layout
Physical Design : Placement / Layout : Cell-Based ICs
Physical Design : Placement / Layout : FPGAs / PLDs
Physical Design : Placement / Layout : Masked Gate Arrays
Physical Design : Placement / Layout : MCMs / Hybrids
Physical Design : Placement / Layout : MEMs
Physical Design : Placement / Layout : Mixed Cells & Blocks
Physical Design : Placement / Layout : PCBs
Physical Design : Plotting
Physical Design : Process Migration
Physical Design : Routing
Physical Design : Routing : Cell-Based ICs
Physical Design : Routing : FPGAs & PLDs
Physical Design : Routing : Masked Gate Arrays
Physical Design : Routing : MCMs / Hybrids
Physical Design : Routing : MEMs
Physical Design : Routing : Mixed Cells & Blocks
Physical Design : Routing : PCBs
Physical Verification
Physical Verification : Clock Tree Analysis / Skew
Physical Verification : Crosstalk, EMC, EMI, GndBounce
Physical Verification : Delay Calculator
Physical Verification : Design Rules: DRC ERC LVS
Physical Verification : Electromag Analysis / Modeling
Physical Verification : Electromech Analysis / Modeling
Physical Verification : Fatigue Analysis
Physical Verification : Logic Extraction
Physical Verification : Metal Migration
Physical Verification : Netlist Extractor
Physical Verification : Parasitic/Interconn Plan/Extractor
Physical Verification : Power Analysis / Estimation / Char
Physical Verification : Signal Integrity
Physical Verification : Thermal Analysis
Physical Verification : Timing Analysis
Physical Verification : Vibration Analysis
Synthesis
Synthesis : Behavioral
Synthesis : Clock Tree
Synthesis : Datapath
Synthesis : DSP Architecture
Synthesis : Embedded Memory
Synthesis : Filter
Synthesis : Logic
Synthesis : RTL
Testing
Testing : Analog Fault Simulation
Testing : Design/Synth for Testability (DFT) / BIST
Testing : Digital Fault Analysis / Simulation
Testing : Failure Analysis
Testing : Test Bench Generation / ATPG
Testing : Testabilty Analysis
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