Due to effects such as subthreshold leakage currents, the power dissipation in a submicron static CMOS chip can also be summarized to be related in a nonlinear fashion to the following other factors:

• the symmetry of the input and output transition times,
• the process technology used (e.g., SOI, gas, Si), and
• the transistor dimensions (mainly transistor channel length).

Power Reduction Criteria

As we have just seen in the previous analysis, power dissipation mechanisms are related to four basic parameters found in any CMOS VLSI chip:

• size (or number of gates),
• frequency of operation (or clock speeds),
• voltage of operation (both core and peripheral), and
• technology (the transistor dimensions in microns).

The first of these parameters, size, is an inherent property of using VLSI design techniques in the first place, and we can guarantee that chip sizes, especially in the current wake of SOC design policies, will only increase in the years to come. The number of gates in any design can, however, be controlled by careful design strategies.

The second parameter, frequency, will also follow the common trend of increasing in the future. Design techniques can be applied here to reduce speed by trading for gates (parallel design, heavy pipelining) and adding intelligent control: activity sensing, on/off control at module boundaries, external activation and deactivation of portions of a chip, say by interrupt and/or register control bits.

The third parameter, voltage, will also follow a common trend, which is to reduce. How far depends on the technology used and a device's application and environment. We have seen reductions from 5 V to 3.3 V, 2.5 V, 1.8 V, and more recently to 1 V. How low we can actually go depends heavily on clever circuit design techniques enabling lower noise margins to be tolerated.

The fourth parameter, technology, will follow scientific breakthroughs, but also follows the common trend of getting smaller. How small depends mainly on process technology and innovations in physics and chip design. We are now down to about 0.1 µm.

If we are serious about saving power in a design at the system level, then we must concentrate on reducing both a chip's operating frequency(ies) and its operating voltage(s), as these are really the only two parameters as a user of a chip we have power over. On another level of granularity, the question becomes "How many nodes are actually switching in unit time?" Obviously this figure is going to be application-dependent, but typically a significant number of nodes will always be switching to perform some measure of work (or else what are we designing…an electronic shoe box?). However, when a unit is not being used, a major saving could be made by powering it down completely. This is really a software or firmware issue, unless automatic hardware activity detection is built into a chip. The Blackfin™ DSP attempts to address all of these issues, and achieves some measure of success in each area as we shall see in the next article.

Conclusion

Lowering power dissipation is a key criterion when designing modern ultra high speed, often massively parallel, very high gate count VLSI chips. These design techniques become paramount when applied to portable computing and communications devices.

References

Kaushik Roy and Sharat C. Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley and Sons, 2000.

UCSC Extension VLSI Design Course, Low-Power VLSI Design Techniques, 2000.

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