ADI's New Blackfin™ DSP Page 1 of 2

Part 2: Power Consumption
by Dr. Barry Henderson

Introduction

As discussed in my last article, ADI's New Blackfin™ DSP—Sailing Above the Chop, the new Blackfin™ DSP family from ADI promises to deliver on many fronts. One active and fertile area of research is of course that of power consumption—or rather the lack of it. Another area, especially relevant for a dual processor such as the Blackfin™ DSP family, is the ease and efficiency of programming. I will discuss the first of these subjects, power consumption, in this article and the next one. A later article will then deal with the issue of programmability.

The power consumption hotspot has been gaining momentum gradually over the past few years. The fundamental goal here is one that should, at some level, concern us all. Basically the goal is that it is always a good thing to reduce power consumption. Consumer and industrial device power consumption (read component power consumption here) has a direct effect on the amount of power that actually needs to be generated. The more efficient the devices are, the more efficient the equipment built with those devices will be. Of course, if such an aim makes devices smaller and more powerful (and hence cheaper due to the natural tendency to integrate more stuff on a chip), then we may sell more of them…which means yet more power consumption! However, enough speculation…

The Basic Principles of Low-Power Design

One good question to ask when trying to provide an objective analysis of the pros and cons of the power-sinking attributes of a new DSP (or in fact any other electronic device) is "What would a realistic ideal chip be capable of doing?" The word realistic in the previous sentence promotes the idea that zero power consumption will never be an option. Superconducting DSPs at room temperature are, I believe, a ways off yet! It also directs us to emphasize results obtainable using modern existing technology, which in the case of a Blackfin™ DSP is static CMOS logic.

Another path that could have been taken by the Blackfin™ DSP core logic designers would have been to design the chip using dynamic logic. Dynamic logic offers several advantages over static logic, the main one being speed. However, the disadvantages of designing with dynamic logic (i.e., the lack of readily available high-quality tools, little-proven track record, and greater susceptibility to noise due to lower noise margins) have largely precluded it from mainstream applications. Dynamic logic does make a brief appearance in the Pentium Processor, to name one, mainly to improve the performance of critical-path logic. The problem with dynamic logic is that even with zero activity each node still has to go through its precharge and evaluate processes. Statistically this would mean that about 50% of the nodes would still be switching, even when functionally this activity was totally unnecessary. It can therefore easily be seen that power consumption (or the reduction of it) is definitely not a strong point of dynamic logic!

Major Mechanisms of Power Consumption in Static CMOS Logic

Any static CMOS chip really has three major mechanisms that contribute towards power consumption. The first is called static power consumption. In CMOS logic, this is really quite trivial because the static current is reduced to the leakage values of CMOS transistors during stable states (when there is no switching activity). This is because one or more transistors (either n or p, depending on the logic configuration) will always be off for each DC path in each circuit loop. With modern design techniques in VLSI technology, the leakage current of an n or a p transistor is a few (i.e., n) femtoamps (I_leakage = n × 10^-15 A).

However, with VLSI chips now integrating several tens of millions of transistors onto a single die, the summation of this leakage current across an entire chip is becoming more significant, but it is still a small amount when compared to other mechanisms (i.e., a few µA perhaps). The following power dissipation analysis and equations are derived with respect to typical CMOS gate structures (e.g., the inverter shown in Figure 1).

Figure 1 - CMOS Inverter

In Figure 1 the NMOS gate is assumed to be on whenever V_in > V_nth (where V_nth is the NMOS threshold voltage) and off whenever V_in £ V_nth. The PMOS gate is assumed to be on whenever V_in > V_pth (where V_pth is the PMOS threshold voltage) and off whenever V_in £ V_pth. The values of threshold voltages and input signals used here are both absolute magnitudes.

The assumptions made above are not entirely accurate due to leakage currents, especially when using very short channel transistors, as is the case in state-of-the-art VLSI chip design where l < 0.35 µm (we are now at l < 0.13 µm). In modern VLSI chip design (l < 0.35 µm) leakage currents can increase approximately exponentially due to subthreshold leakage effects. This is caused by nonlinear behavior in small-channel-length transistors.

The subthreshold leakage effect is a complex process that depends on factors like threshold voltage, subthreshold swing, operating voltages, process technology (e.g., Silicon on Sapphire, SOI, offers good subthreshold swing and so has an advantage over silicon for low-power design) and several other design parameters. Due to subthreshold leakage effects, static power dissipation in deep-submicron VLSI chip design is now becoming a much larger factor in the power-dissipation equation than before.

Equation (1) shows how static power consumption relates to the total chip leakage current and power-supply voltage, V_p.

P_static = V_p × I_{total_leakage}

(1)

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