ADI's New Blackfin™ DSP

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 Part 3: Powering Down
 by Dr. Barry Henderson

Power Management Analysis
Now that we have a good overview of the dynamic power control capabilities offered by the ADSP-21535 and associated members of the new Blackfiný DSP family, it is time to analyze the benefits and gains provided by them. One useful approach may be to design a systems firmware structure so that on reset the DSP performed only a brief set of system initialization functions, after which the DSP enters sleep mode. Then the firmware would only 'wake up' specific blocks {in real time} as they become essential to the systems operation. An indication of when and which modules must execute could either be based on an internal event {i.e. a timer timing out}, an external interrupt, a state machine, or more likely a combination of these three mechanisms. Figure 3 illustrates this kind of software based power control algorithm.

Immediately after initialization has been finalized we should force the DSP to enter either sleep or deep sleep mode. Sleep mode can be exited by either the occurrence of a peripheral event {generating an interrupt say} or by a timeout event upon which a specific re-enabling sequence of instructions would be executed. The DSP would then transition quickly either to full on {assume PLL pre-programmed, on but disabled}, active, or relaxed mode depending upon how critical the required activity is. After the event has been serviced and all associated processing completed, the DSP would transition back to sleep mode. Deep sleep mode can only be exited by a reset or an RTC event, and would then take several clock cycles to enable and stabilize the PLL from its off state. This mode would only entered when we know that processing events are going to be absent for a prolonged time period.

Each essential operation would then be performed at the slowest feasible clock speed. This would mean trying to run the DSP with the PLL turned off in either the processors relaxed or active modes whenever possible, to maximize power savings. In relaxed and active modes the actual DSP clock speed is a mere fraction of its normal operating frequency {and Power}, i.e. CLKIN/2. Substantial benchmarking and code profiling may well be necessary to ensure that all timing criterion are still met when processing each event.

Conclusion
Power control, if inherently facilitated by a DSP's architecture, can provide considerable power saving benefits, especially for battery powered operation. The Blackfiný DSP family has been designed with this objective in mind. By designing an intelligent firmware control structure around a Blackfiný DSP, a systems dynamic power consumption can be fine tuned, using layered control, to provide just adequate processing needs. In other words, a systems 'live ness' becomes a function of a request - response type of mechanism. My final article on dynamic power control will discuss this topic in greater depth.

References
The Blackfiný DSP ADSP-21535 manuals can be located at:
http://www.analog.com/library/dspManuals/21535_manual.html

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