ADI's New Blackfin™ DSP

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 Part 3: Powering Down
 by Dr. Barry Henderson

Introduction
In my previous article, I discussed the physical processes that account for the majority of power consumption occurring in modern static CMOS ASIC's. I also highlighted the major important factors when designing for low power. This article takes a closer look at how the Blackfiný DSP architecture achieves at least some of these goals.

Low Power Architectural Features of The Blackfiný DSP
The architects of the Blackfiný DSP family have designed in several features to allow power consumption to be controlled by a user. Yet the best is probably still to come. The first device in the family, the ADSP-21535, still requires an external voltage controller to tweak the supply voltage to the chip. Later devices in the Blackfiný DSP family will probably incorporate this control on chip. The chip has 3.3V compatible I/O and a 0.9V to 1.5V core.

Major Chip Features
Figure 1 illustrates the major blocks which contribute to power consumption in the ADSP-21535. The following discussion will highlight the features available to minimize power drain in each block. Basically the chip offers a host of serial communications ports, a Real Time Clock and Watchdog timer plus several programmable timers, a 32 bit 33 MHz PCI bus, a USB bus, a sophisticated DMA engine, a dual 300 MHz DSP processor core {which includes 308 Kbytes of on chip SRAM}, and a Dynamic Power Management {DPM} module.

Clocking
The main clock input to the ADSP-21535, CLKIN, serves to generate both the core clock CCLK and the system clock SCLK. The actual clocks obtained at power up are a function of the logic levels applied to several input pins. The system and core clock rates can also be changed by software dynamically via a number of programmable registers. A 1x to 31x multiply {using an on chip PLL} can be applied to the input clock signal CLKIN to generate the core clock CCLK. The core clock can then be divided down to provide the system clock SCLK, which is used to drive much of the DSP's peripheral circuitry and connecting busses. Table 1 summarizes the clocking features offered by the ADSP-21535 chip.

The main clock input to the ADSP-21535, CLKIN, serves to generate both the core clock CCLK and the system clock SCLK. The actual clocks obtained at power up are a function of the logic levels applied to several input pins. The system and core clock rates can also be changed by software dynamically via a number of programmable registers. A 1x to 31x multiply {using an on chip PLL} can be applied to the input clock signal CLKIN to generate the core clock CCLK. The core clock can then be divided down to provide the system clock SCLK, which is used to drive much of the DSP's peripheral circuitry and connecting busses. Table 1 summarizes the clocking features offered by the ADSP-21535 chip.

Dynamic Power Control
The clocking arrangement for the ADSP-21535 shown in table 1 above provides a reasonable range of speed options for controlling dynamic power consumption by altering the clocking frequency applied to the two major blocks {Core and Peripheral}. The ADSP-21535 has five operating modes which are summarized in table 2. This programmability allows for varying degrees of power savings to be made in a dynamic fashion if necessary. With the PLL {Phase Locked Loop} disabled the maximum value for the core clock is always CLKIN/2, giving a range from 5 MHz to 16.5 MHz. The system clock is again found by dividing the core clock by the value programmed into a register which generates the Dv value.

Figure 2 illustrates the power control layering provided by the Blackfiný DSP. We have quite fine control over both core and peripheral logic clocking frequencies, and also fine control over both the core voltage supply and the peripheral voltage supply {excluding PCI, PLL and the RTC}. Another opportunity to control power consumption is provided by the Blackfiný DSP architecture. That is the capability to dynamically enable and disable specific blocks of peripheral logic {e.g. PCI, USB, Serial ports}. This hardware/firmware control framework provides us with many opportunities to design a system which can respond intelligently to different operating conditions.

References
The Blackfiný DSP ADSP-21535 manuals can be located at:
http://www.analog.com/library/dspManuals/21535_manual.html

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