Page 2 of 3

The data used in these computations are shown in Table 1. Basically I preset three realistic activity levels, each of which represents (an increasing) level of liveness for the DSP and its associated peripherals.

Table 1 - DSP Power Consumption Data

Activity Level		0.1	0.1	0.5	0.5	1.0
f (MHz)		10	33	100	200	300
Vcore	Vcore²	Power1	Power2	Power3	Power4	Power5
0.9	0.81	0.81	2.673	40.5	81	243
0.95	0.9025	0.9025	2.97825	45.125	90.25	270.75
1	1	1	3.3	50	100	300
1.05	1.1025	1.1025	3.63825	55.125	110.25	330.75
1.1	1.21	1.21	3.993	60.5	121	363
1.15	1.3225	1.3225	4.36425	66.125	132.25	396.75
1.2	1.44	1.44	4.752	72	144	432
1.25	1.5625	1.5625	5.15625	78.125	156.25	468.75
1.3	1.69	1.69	5.577	84.5	169	507
1.35	1.8225	1.8225	6.01425	91.125	182.25	546.75
1.4	1.96	1.96	6.468	98	196	588
1.45	2.1025	2.1025	6.93825	105.125	210.25	630.75
1.5	2.25	2.25	7.425	112.5	225	675

Notice in Figure 1 that the square law nature of Equation (2) does not appear to be very pronounced. This is due to the fact that V_core is either below, at, or just above 1.0 across the whole range of operation. A generalization can be inferred here, as the trend is for chip voltages (especially for complex high-speed cores) to fall to 1 V and below in the near future. With V_core < 1.0 V, the power consumption is actually reduced because of the square law relationship.

We can thus determine that Equation (2) approximates to a linear relationship between power consumption and core supply voltage when V_core is at or around 1 V. This may well turn out to be the typical case for Blackfin™ DSP applications. The only exception is when an application demands peak operating capability (V_core @ 1.5 V).

Activity Levels

Activity Level 1 (0.1 or 10%) represents the case where the majority of the chip is in sleep mode. Activity Level 2 (0.5) implies that 50% of the chip (including its peripheral drive circuitry) is in an active state. In Activity Level 3 (1.0 or 100%), the chip is fully functional and is operating at its peak performance with the core, peripheral voltages, and clock frequencies at maximum.

<< Previous

Next >>

Real-Time Processing Using DSPs, FPGAs & uCs Archive

Guides and Experts   Analog Avenue   EDA Tools   PLD   DSP   EDA   Embedded Systems   Power   Test

		Click here to get your listing up.