ADI's New Blackfin™ DSP

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 Part 4: Analysis of Dynamic Power Consumption
 by Dr. Barry Henderson

Introduction

In this article (the penultimate article dealing with dynamic power), I will present a detailed analysis of dynamic power consumption based on the Blackfin™ DSP family. We will see the type of savings that can be made by using the power-control features provided by modern processors such as the Blackfin™.

Still to Come…

The final article on dynamic power will describe the major factors that modern designers use to focus their efforts to produce systems with scroog-like power consumption while still maintaining adequate levels of performance to drive modern signal-processing-based systems (e.g., multimedia, communications), and will generalize and summarize the findings made during this short series of articles about dynamic power consumption.

Preliminary Details

One factor to note first is that architectures such as the Blackfin™ DSP have been designed to satisfy as wide a range of applications as possible within a broad sphere, and so must add the ability to cater for a wide spectrum of system design features.

For example, to etch out a useful market place, the Blackfin™ DSP family (among others such as TI's C5000) must provide the capability to interface to various types of memory (SRAM, SDRAM, flash, etc.), and many different peripherals (PCI, USB, USART, etc.) while providing the ability to process copious amounts of data in short order…read: lots of MIPS with minimal power drain. Meeting typical standard core and I/O voltage levels is also another salient factor. The architecture is thus initially constrained by having to cater to so many, often conflicting, design goals.

Blackfin™ DSP Power Control Features

Remember from my previous article that the major equation that dominates the dynamic power consumption of a static CMOS device is

Pd = C Vp² f	(1)

The Blackfin™ DSP architecture gives a system designer control of two of these parameters—the power-supply voltage V_p, and the clock frequency, f. The load capacitance C at each I/O pin is also under a designer's control at the board-layout level. Peripheral-device voltages and clock frequencies are typically defined by a standard and cannot be tweaked very far when active. The clock frequency can be controlled at two levels—the module level and the global level. At the module level we can enable and disable specific blocks (e.g., PCI controller, USB controller, DMA) using intelligent firmware to decide if and when each chip feature is required to be active.

Such decision-control logic would probably be embedded in firmware coupled to an interrupt-driven request/response mechanism as previously mentioned. At the global level we can control and scale both the core clock and peripheral clock frequencies over a fairly broad operating range, as described previously. We can also program the core operating voltage over a fairly wide range, and the peripheral operating voltages to some extent if desirable.

As a chip's power consumption scales to the square of the operating voltage, this should provide a fairly large power saving. How large though? Referring to Figure 1, which shows typical operating voltages and frequencies for a Blackfin™ DSP, we can determine that the core voltage V_core can be reduced to its minimum value when operating in reduced-load situations, and CLKIN can also be reduced to its lowest clock frequency. This scenario assumes that other constraints (having to supply specific clock frequencies to peripherals such as PCI, USB, memory subsystems, etc.) do not exist.

click for larger image

Figure 1 - Blackfin™ DSP Dynamic Power Dissipation Curves

Blackfin™ DSP Power Consumption Estimates

The power consumption levels (Power1 to Power5) shown in Figure 1 were derived from Equation (2) (the capacitive loading C is actually arbitrary here and is set to 1 for convenience since all the calculations here are relative anyway).

Power = Vcore² × f × C × Activity Level	(2)

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