Intel's Itanium Processor
by David Gilbert

The Intelý Itaniumý processor will be released in production quantities soon, and there has already been much talk about the design. Even before first silicon, there was speculation about the forthcoming IA-64 architecture. Let's take a look at the "roots" of "Merced," and use this perspective to view this chip's part in the larger picture of microprocessor architectural evolution.

Introduction
Over the past several years, Intel has managed to achieve an economy of scale with its 32-bit PC processors. By continuing to utilize the basic building blocks of the P6 micro-architecture that was initially developed for the Pentium Pro chips of 1995, Intel was able to create versatile processors that pulled double duty in home PC's or low-end business servers.

As time passed, the company sought to differentiate its products in order to target the diverse market segments such as low-end and high-end PC's, workstations, and servers. Therefore, in addition to the Pentium II, we had the Celeron and Xeon processors coming onto the scene.

By the time that the Pentium III shipped in quantity, Intel had asserted its dominance in the area of home PC's and low-end servers against competitor Advanced Micro Devices. The market for workstations and high-end servers was not that simple, however. In order to capture the majority of market share in a segment that has been ruled for years by IBM, Sun Microsystems, Hewlett-Packard, and SGI, there would have to be a more complete differentiation of the Intel Architecture.

The Competition
The RISC architecture has embodied the world of high-end computing practically since the distinction between CISC and RISC was made. Every manufacturer involved in supercomputing or high-performance workstations and servers has fielded a RISC chip, and their complexity has continued to increase.

There came a point where some people believed that this trend called into question the premise behind the entire RISC architecture, and alternatives were sought. IBM, and others, pursued research in the field of VLIW systems due to their promising yields in instruction level parallelism. The barriers to successful implementation that VLIW faced, however, were greater than what most engineers were prepared to attack. As a result of this, and other factors, the development paths of RISC and VLIW remained distinctive and the performance gap between the IA-32 architecture and RISC processors continued to grow.

One Answer
It seemed that the only way for Intel to make an authoritative entry into the high-end market segment would be to introduce a completely new architecture. This represented too great a challenge because of the need to maintain backward-compatibility with existing IA-32 code and because of the time-to-market constraints that exist in this industry. Some sort of compromise was in order, and the clear solution would be to implement a hybrid architecture that carried forward the best attributes of VLIW and RISC, while maintaining hardware compatibility with the previous 32-bit designs. How to get from here to there is where varying degrees of innovation and determination would mean the difference between success and failure for Intel.

Many Questions
The Itanium was crafted principally as a VLIW chip, with some elements of RISC thrown in for good measure. What this meant, in terms of design complexity, was that new hurdles would be introduced that no one had as yet faced.

The importance of known variables was not to be overshadowed, though. For instance, an advanced compiler would have to be developed, and this type of endeavor often took years to complete, effectively. The chip would possess many functional units and a complex pipeline, as well as full 64-bit capability, but if software vendors could not write applications that took advantage of these new features, then all would be for naught. And if there weren't an adequate number of reliable operating systems that would run on it, then everyone would be wasting their time.

The Who And The Why
In a capitalist economy, market forces serve as motivation for innovation and change. Going into the 1980's, each of the major computer companies was sustaining its own architectures, which necessitated an infrastructure of proprietary operating systems, compilers, I/O, and networks. This paradigm changed to a standards-based model, in the likeness of the IBM-PC market, and it became clear that further research and development was needed to leverage previous efforts. This, coupled with the dramatic increase in complexity that RISC architectures were seeing in the early 1990's, set the stage for an unlikely alliance.

Hewlett Packard was one of several companies investigating the VLIW architecture, in an attempt to find a successor to their large installed base of RISC systems. However, because of the need to support its customers, the HP project came with a string attached: backward compatibility with PA-RISC. Intel was also in need of a new architecture, and halfway through 1994 they entered into an agreement with Hewlett Packard to pursue the future of high-performance processing. This partnership was necessary for both companies in order for the results of their work to transcend the barriers of entry and become a new de facto standard, if not an industry standard.

The What And The How
Hewlett Packard and Intel use the acronym EPIC to describe the IA-64 architecture; this stands for Explicit Parallel Instruction Computing. Aside from the full 64-bit memory addressing capability, the most striking thing about IA-64 is its attention to parallelism through VLIW techniques.

In terms of functional units and resources, the Itanium is quite an arsenal. There are two load/store units, four integer units, and two dual-pipe floating point units. The chip also has 128 general-purpose registers and 128 floating point registers, with a mechanism called the Register Stack Engine that allocates data to them. These registers are 64-bit. Special function registers include a means of flagging data dependencies within the instruction stream, and a method for maintaining compatibility with previous architectures in hardware.

The Register Stack Engine (RSE) is one of the primary features of IA-64, and it represents a new method for allocating and managing the contents of registers. To be more specific, the 128 registers of the Itanium are organized into "static" and "stacked" subsets, and only the first 32 are static. The size of the stacked subset can vary, up to a maximum of the remaining 96 registers, and this is done by renaming the register addresses. The structure of the stacked subsets is further broken down to enable micro-management of these resources.

Other key features of IA-64 are implemented in the compiler, which must be specialized. This is where branch hints, explicit parallelism, register stack rotation, predication, and speculation occur. None of these concepts in particular are new to the computing industry, but the EPIC platform will mark the first instance of combining all of these performance enhancements in one architecture that was designed from the ground up to incorporate them.

Conclusion
We live in exciting times, and Hewlett Packard and Intel are heralding the EPIC platform as an entirely new micro-architecture. Some say this creation is analogous to the creation of RISC from the shortcomings of traditional CPU designs in an earlier time. The truth of the matter is that without RISC or VLIW or CISC we wouldn't have EPIC at all. This series of chips (there are 5 IA-64 chips in various stages of development) is standing on the shoulders of a heritage that has existed for more than twenty years, and continues to grow even today.

To the credit of those who worked on this long endeavor, EPIC has achieved a leap forward in efficiency, capability, and throughput that may very well be unrivalled. Time awaits the introduction of Advanced Micro Devices' K-8 for confirmation of this, however. Within this brief discussion of the EPIC design, it is clear that I could no more than scratch the surface of this wonderful piece of work that represents the culmination of more than 6 years of dedication by hundreds of engineers from dozens of companies.

Additional Reading
www.intel.com (Intelý Itaniumý processor)

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