Hardware Software Co-Design/Verification, Part I - HW SW Modeling

As advancements in ASIC design methods and EDA tools revolutionize chip design, new embedded IP and system design techniques revolutionize both system and chip design. Embedding processor and DSP cores within chips with major software functions calls for system level tools for system and chip architecture development, HW SW tradeoff analysis, and System-On-Chip design implementation. System designers have used instruction set simulators and high level modeling languages, particularly C, for many years. Several commercial companies have developed proprietary languages and simulation or modeling products to support their languages. In this article you will see a dialog of whether C should be the language of choice for HW SW Co-design or whether a new bridge language for HW SW definition is a better solution. EDA tool companies are racing to meet the opportunity for new tool solutions. The 1999 Design Automation conference was alive with advancements in EDA products for system level design with a substantial presence of both established and start-up EDA companies willing to show their capabilities. We provide a matrix of companies, their products, and tool functions shown at DAC, and a glimpse at how representatives and experts from EDA companies expect that the industry will meet the need for improvements in HW SW Co-Design/Verification.

Company	Products	Functions Represented in Tools	Web URL
Cadence Design Systems	Cierto Virtual Component Co-Design (VCC)	A behavior diagram for specification An architectural diagram A mapping process Performance models for performance simulation Software estimation that creates a performance model A simulator An analysis environment Links to implementation tools	www.cadence.com
Mentor Graphics	Seamless CVE	HW/SW Co-verification Virtual prototyping Coherent Memory Server (patented) Dynamic Optimizations N-Processor support Open simulator API Open debugger/ISS API Seamless Plug-In Interface Widest range of supported CPUs Widest range of supported DSPs Comprehensive modeling Processor Integration Kit SOC Verification Hub Co-Design tool integration Intelligent testbenches	www.mentor.com/seamless
Synopsys	Eaglei	Supports most popular processors; ARM, MIPS, MPC,PPC, Intel, Fujitsu, Hitachi, NEC, Toshiba, TI, ST, DSP Group, IDT, LSI, etc.. User-definable levels of optimization for performance and accuracy Design flow integration with other Synopsys verification and co-design tools for SoC support,including MemPro memory model generator for HW memory and VERA testbench automation tools Open environment supports popular HDL simulators, software IDEs and RTOSs, HW accelerator and emulator technologies Full debug visibility and support for HW and SW at all abstraction levels; C, behavioral, RTL and Gate Direct "Peek/Poke" capabilities from memory window in SW IDE or Eaglei console Supports multi-processor designs All features supported across a network and platform distributed co-verification environment for Solaris, HPUX and NT	www.synopsys.com
Co-Design Automation	Superlog	System - interface, protocol, stae machine, queue, inferencing, elaboration Software - dynamic processes, recursion, arrays, structures, I/O library, pointers (From C, Java) Hardware - events, timing concurrency, multi-valued logic, tasks/functions, sequential / combinational logic (From Verilog, VHDL	www.co-design.com
Summit Design Automation	V-CPU Pro SW/HW Co-development Environment	High performance environment allows "co-development" of software and hardware surpassing first generation co-verification environments Access to Real Time Operating Systems (RTOS) Software Functional Models (SFM) speed simulation throughput by allowing hardware to be written and simulated in C outside of logic simulator	www.sd.com
CoWare N2C Design System	N2C Design System	Executable specifications C/C++ based open system Functional and performance modeling Automated interface design for IP Hardware design by refinement in C C-to-HDL automation , HDL import C-based virtual prototypes Complete co-design flow	www.coware.com
CAE-Plus	RTL2C, ArchGen, ASVP Builder	Translates HDL to RTL-C Captures the behavior graphically Synthesizes the RTL design and C models Integrates the C models created by RTL2C and ArchGen with verification and debugging software	www.cae-plus.com
Arexsys		Co-simulation backplane tool Architecture Exploration for HW/SW Partitioning from system level descriptions Code generator for conversion to hardware RTL and software C	www.arexsys.com
C Level Design System Compiler (C2HDL)	System Compiler (C2HDL)	Full ANSI C support for both RTL and Behavioral Design VHDL and Verilog Output Multi-module level hierarchy in C and HDL simulations Pipelining and concurrency in C	www.cleveldesign.com
Frontier Design	AIRT "Algorithm-to-RT" Builder Architectural Synthesis Toolkit	C-based system-level design including HW-SW co-design, interface synthesis, and IP re-use. Automatically converts C code to Verilog or VHDL Supports fixed-point data and operators Built-in functions for bit manipulation Automatic "dontcare" initialization of non-static variables Automatic testbench generation Supports third-party synthesis tools Available on Hewlett-Packard, Sun and Windows NT workstations	www.frontierd.com
LavaLogic	Forje-J		www.lavalogic.com
VaST Systems Technology	CoMET	Interactive hardware/software tool set for systems-level design Executes application software on retargetable Virtual processor Models Models supported include: ARM, Hitachi, Intel, Motorola, MIPS, SPARC Can be linked to Mentor Graphics Model Technology, Cadence, Synopsys, and Fintronic Simulators Supports C and C++ for software Supported on Windows NT and Solaris Platforms	www.vastsystems.com
Nu Thena Systems	Foresight Co-Design System	Simulation and modeling environment for SOC design Fully synchronized multi-level abstraction co-simulation with Mentor Graphics Seamless CVE and Modelsim Supports VHDL, Verilog, C, and C++	www.nuthena.com
TransModeling	System Modeler	SLDA too for developing high-speed C or C++ models and test benches Interchanges HDL and System models transparently Allows for distributed, parallel HDL simulations within system level environment

Experts of representative companies were asked to share their vision for HW SW Co-Design/Verification a few years into the future. This is what they had to say.

"System designers are realizing that in order to adopt an effective HW/SW system design methodology a new set of tools are required that can utilize abstract system specifications. Tying the specification to design implementation is the key to solving the "system in silicon" problems of design reuse, early access to virtual prototypes for software development and automated transformation from specification to hardware and software. Over the next two years, design creation, analysis, verification and synthesis tools will become available and mature enough to support high level system design and the methodology necessary for improving HW/SW co-development productivity."

Charlie Loegering, VP New Business Development, Summit Design Automation

"Successful companies will be designing at the system level, supported by an increasingly automated RTL implementation flow. Interface synthesis will make plug-and-play IP a reality. The hardware and software teams will be tightly integrated, using C/C++ as a common design language. Early hardware-software integration will eliminate the current system verification bottleneck."

Nick Lethaby, Technical Marketing Manager, CoWare, Inc.

"As for the future of HW/SW design, I believe that to enable true co-design between hardware and software teams, it is imperative to have both groups using the same language. It is the only way to facilitate rapid design iterations between the two groups. By supporting ANSI C which is the universal language used by software developers, hardware designers now have a common design language to work with software developers that also links seamlessly with their existing RTL design flows."

David Park, Vice President, Marketing, C Level Design, Inc.

"With the advent of the embedded processor and System-On-Chip (SOC), HW/SW co-design has become a mandatory part of the design flow. This need is driving a change in methodology, for which the only solution can be a design language capable of supporting architectural, HW and SW design together. True SOC requires the cooperation of different design specialization's, and they must all be talking the same language for success."

David Kelf, Vice President, Worldwide Marketing, Co-Design Automation

"In two years hardware/software co-design will be a necessity, but it will be merely part of the solution. Co-design must be combined with co-verification, simulation, architectural assessment, realization and specification. In short, a systems engineering methodology, fully integrated from start to finish, is needed to successfully address increasing chip complexity and shrinking market windows."

Dr. Graham Hellestrand, Chief Executive Officer, VaST Systems Technology

"The drive toward systems on a chip (SOC) designs is forcing developers and suppliers to view software as an equal partner with hardware in the design. This will require a transition toward higher levels of abstraction in the design process and a marriage of hardware and software at all levels of the design and verification process.

The resulting methodology and process flow will encompass high-level system design, partitioning, code generation, and handoffs to hardware and software design teams. These teams will then need to continue the HW/SW methodology down through detailed functional and timing verification. The flow will allow for continuous, contiguous design and verification at all stages of the design. This could be called the "early and often" co-design/verification flow."

Ellie Burns, Eaglei Product Marketing Manager, Synopsys

Copyright Summit Innovation Inc, 1999

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