With emulation, a fabricated chip may be accessed within the design environment. Also an entire ASIC or subset such as a core, may be temporarily modeled in FPGA hardware inside an emulator box or with a specially FPGA populated printed circuit board. The debug process with emulation includes access to logic and circuits implemented in hardware. Test and measurement instruments may be used for debugging the design with the hardware implementation. For some solutions, a logic analyzer operates with industry available debuggers for tracing down software and logic errors, and an oscilloscope helps find analog circuit errors.

The software modeling method can be applied sooner in the development process if we assume that an ASIC or IP core development methodology favors simulation of both already designed functions and design in-process functions with robust software models. Some developers favor a quick hardware implementation in FPGAs to begin a hardware based verification process. In the first case the tools of the type listed in "Part 1, HW SW Modeling" would be useful. In the second case the tools listed below would offer debug capabilities of most interest to the development team. In each case the methodology brings together experts in software and hardware with what might be considered a bridge set of tools for both disciplines.

The ongoing concern with HW SW modeling is model accuracy. Does the model provide simulation visibility of all bugs and design issues that a developer would uncover with a pre-production version of the product? The concern with hardware emulation is whether the interconnections used for emulation, on and off chip, are different enough from that in the final manufactured product to not accurately reflect the production version after the chips are fabricated and the test fixtures utilized for emulation are disbanded.

Factors such as whether the design project is an enhancement of a current design, or whether it is a major new design with some reuse, and the degree of complexity of the system and chips to be designed, affect the choice of a hardware software co-design/verification tool suite.

We provide a matrix of companies, their products, and tool functions. Representatives and experts from product suppliers have also provided their view of the future trends in hardware software co-design and verification.

"Chip applications are moving quickly to SoC capability wherein embedded processors with application specific software will dominate both the ASSP and ASIC worlds. The principle bottleneck in shipping product will be verification of these complex system chips. Emulating these chips at MHz speeds in a form factor that provides visibility into the various IP blocks, custom logic, and block interconnect for hardware debug and visibility into internal registers with standard software development tools will be essential. The risks of not emulating such complex chips is simply too great."

Ralph Zak, Vice President Marketing, Aptix Corporation

"Over the next two years, as more design teams move to high-end RISC processors and silicon systems, we can expect to see more debugging features and even real-time analysis modules integrated into the silicon. In-circuit debugging and real-time analysis will be accomplished through access ports provided by the silicon manufacturer."

John Marshall, Hewlett-Packard Logic Analysis System Marketing Manager

"Embedded System will dominate future designs in telecom applications. We are also starting to see new System on Chips being designed that look nothing like the traditional designs of today. Such new designs consist of one or more microprocessor cores, one or more DSP cores, both resulting in more that 30% of the die size, one to two megabyte on-chip memory structure, some number of pre-existing IP blocks and relative small amount of new logic designed specifically for this system. The new logic, less than 30% of the die size is new functionality, that was chosen to be implemented in hardware plus the logic that ties together the collection of the mentioned IP blocks, memory structures and large amount of embedded software."

Gabriele Pulini, Marketing Director-Meta Systems Division, Mentor Graphics Corporation

"As System on Chip (SoC) design teams are enhancing their verification methodologies to include HW SW co-verification, significant demand for emulation performance is emerging. Emulation is one of the few verification platforms that has the performance to make running software and real system operation viable. IKOS is supporting the use of emulation as a key component in SoC verification by offering the most aggressive roadmap in the emulation market - delivering a new emulation platform that is at least 2x gate capacity and 4x memory capacity every 12 to 18 months. IKOS just released our 3rd generation emulator VLE-5M with 4.5M gates and 48MBytes of memory. Each machine has also reduced the cost per gate with the VLE-5M selling currently selling for $0.37 per gate US list price. This coupled with innovative work we are doing in software to provide 100% visibility and a transaction level C-interface, IKOS is making great progress toward getting the performance and power of emulation onto the engineer's desktop to accomplish system-level verification of both hardware and software."

Larry Melling, Vice President Marketing, IKOS Systems, Inc.

"As designs become larger and more intellectual property cores are combined to create large Systems on Chip, the need for high performance system level verification is critical. Only hardware emulation provides the performance necessary to execute enough embedded software and run enough hardware clock cycles to verify correct behavior of the design. As we look forward over the next two years, we see emulation technology as the underlying platform that allows the design team to bring together IP cores, newly designed ASIC logic and software AND run the system at hardware speeds AND interact with real world external stimulus. Availability of IP models, integration of software and hardware debugging tools will help design teams create and debug systems faster. Perhaps the greatest challenge is modeling the world outside of the system. Modeling a set-top-box SoC design for example, requires the ability to process baseband data from a satellite receiver, process the data and extract and display high resolution video in real time. The designer can then interact with the design to make sure the all video manipulation functions such as data decompression, picture-in-picture management and audio processing work properly. Emulation becomes an essential underlying technology for modeling not only the SoC design itself, but the environment around the chip."

George Zafiropoulos, Director Strategic Marketing, Quickturn a Cadence Design Systems Company.

Copyright Summit Innovation Inc, 1999

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