The Search for a Breakthrough in IC Design Productivity

The measurement of design productivity has been illusive for some time. Should the measurement be linked to design cost per transistor or gate? Should it include test program development? Should the measurement include the time spent in proving that the IC operates properly in the system prototype? Some are satisfied to compare new projects to previous projects, but consecutive projects are seldom similar. How should design re-use of intellectual property (IP) cores affect the measurement? "Re-use" may encompass not only the re-use of the design itself, but also the re-use of a verification test bed from a previously designed chip.

To fund the development of new chips, budget estimates are expected. The estimates are likely based upon prior cost experience and projections considering the development techniques to be used for the new projects. Dr. Hector de J. Ruiz, President of Motorola's Semiconductor Products Sector speaking at DesignCon98, estimated that when all aspects of product development costs for system on a chip are considered, including costs of customer interaction on requirements, embedded software development, etc., Motorola's current cost is approximately $16 per transistor. If design productivity were not to improve, the development cost for 300-to 400-million-transistor leading-edge chips, designed in the next decade, could approach $5 to $8 billion for each chip. Dr. Ruiz noted that a development cost of this magnitude is close to the estimated R&D cost of a jumbo jet aircraft. Motorola's goal is to double design productivity every 24 months. The search is on for a break-through in design productivity.

The factors adversely affecting IC design productivity are the rapidly increasing chip complexities, and the unexpected deep submicron effects requiring evaluation of the routed interconnect and devices for parameter extraction, timing and power analysis. Model and timing-estimate inaccuracies caused by unpredictable interconnect factors have been considered the gremlins causing chip verification to increase from 20% to 60% or more of development time. This has profoundly and adversely affected design productivity and chip development cost. The aphorism, "hurry up and wait," was not coined in the engineering office or laboratory. Nevertheless, due to the increasingly iterative nature of IC design, and the processing, evaluation, and management of large amounts of design data required for each iteration, an engineer may now consider the state of IC design as having hurry-up-and-wait characteristics.

The time to results for each of the functional, physical, timing and power verification processes also contributes to an unacceptably long wait. One or more verification turns at the full chip level in one 8-hour work day improves productivity by two to three times. To achieve multiple verification turns within 24 hours, some engineers telecommute during the night. They submit, review, and re-submit design verification jobs from their homes. To tape out a chip, all of the verification processes must be completed to a satisfactory level. If any one - functional, physical, timing, or power verification - is pending, tape-out is delayed.

The net result is that the creative aspects of design and verification often demand a hurry-up mode, while the compute-intensive processes for verification and the prototyping phases are the wait periods for a design project. When multiple design turns are necessary, the wait periods can exasperate the design team and everyone else who has great expectations for the project. The product design process is further complicated by the temptation to use the wait time to make creative design improvements.

Due to the need to apply verification over much of the design process, the electronic design automation (EDA) industry has experienced healthy revenue gains from products that address chip verification at all levels of abstraction. Indeed, some would prefer to invest more to increase design productivity and create functional value for the customer. Those who make investments in design re-use of intellectual property expect to improve design productivity and functional value. Differentiated functional value may best be achieved by leveraging both industry standard and proprietary intellectual property.

What is on the horizon for improvements in design productivity?
Electronic Design automation (EDA) suppliers and internal development groups are focusing on improving and developing tools to simplify design-reuse. Efforts to standardize internal chip busses, for example, are aimed at improving ease of design reuse. If model accuracy and interconnect prediction were to improve and reduce or eliminate the time-consuming iterative floor planning and timing prediction process, design productivity would be improved. The state of IC design tools and modeling now requires a time-consuming iterative approach to design, with each pass requiring the processing of multi-gigabyte data sets. If power prediction could become accurate at the RTL description, circuit level power analysis could be eliminated or reduced. If semiconductor processes with less interconnect resistance were to become mainstream, predictability of interconnect delay might become more manageable. But, these improvements would be necessary at the same time that chip clock speeds are moving to one GHz. This increase in clocking speed along with reduced process feature sizes raises new design issues with electro-migration, signal integrity, and IR drop.

Are there near-term or immediate solutions?
If iterative design processes must continue in the near-term, could the wait time be considerably reduced with higher capacity electronic design centric processing? New 64-bit UNIXý, operating systems provide much higher capacity processing and eliminate the 4-Gbyte memory-addressability limit associated with 32-bit UNIX systems. Alternative computer processing techniques, such as parallel computing and native compiled code for EDA applications, can also help improve time to results for verification and analysis applications.

Beyond the near term, even if new EDA tool and new semiconductor process solutions lead to a reduction in iterative design steps, the chip complexities of the next decade will require more efficient handling of very large data sets and continually increasing computing power.

Rather than hurry-up-and-wait IC design, new approaches in computing technology are now positioned to return chip development to a more balanced environment for creative design and more efficient proof of design processes.

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