Optimizing Your Design Environment

In this paper, we will first look at the background of some of the tools and methodologies relating to integrated circuit design. Then we will discuss some of the new integrated circuit design challenges that must be overcome. We will proceed with ideas on improving the functionality of EDA tools to solve the current design challenges and make suggestions on optimizing the entire design environment for chip design.

Background

With the arrival of semi-custom design methodology into the mainstream, a little over a decade ago, came new opportunities for electronic designers. The era ushered in the birth of a fledging Electronic Design Automation (EDA) industry and the start up of new computer companies. Chip design was no longer the sole purview of custom chip designers. Application Specific Integrated Circuit (ASIC) design methodology provided the opportunity for system designers to design their own integrated circuits. New design issues, particularly delay in poly-silicon interconnect, were waiting to be conquered. For custom layout designers, depending upon 'software' to place and route circuits was questionable. The Calma system allowed for more touch and expert influence to optimize circuits and area. The EDA industry started with offering simulators and schematic entry tools with a direct path from schematic entry to simulation, considered a productivity breakthrough. Now the EDA industry can take credit for replacing logic design on the back of an envelope with graphical (schematic) entry to language entry, and again back to optional graphical entry of block diagrams, flow charts, algorithmic state machines, and state diagrams. New computer companies were born; some offered both application software and computers. Some had their own unique operating system. Quickly the EDA industry found itself in a perpetual state of consolidation as it continues to be fueled by start-ups. Large computer companies became the sole suppliers of engineering workstations and servers.

We will stop reminiscing, and attempt to place into perspective the opportunities that are available for you to optimize your design environment as you prepare for the first few years of the next millenium. The skills of creating the next product still rest in the minds of the design engineer. Both, the company technologist and the methodologist, are in the spotlight at most companies. They are being asked to sort through and select from a continuous flow of new design automation tools and technology, and to the credit of the same engineer skills just mentioned, select new computing solutions to help electronic designers embark upon, and successfully complete, the next design project.

The New Challenges in Integrated Circuit Design
Effects from Reduced Semiconductor Features

Reduced device and wire sizes in .25mm and .18mm processes bring with them new design challenges. Complex designs for these processes are susceptible to power distribution droop, signal integrity issues, and new challenges in timing management. New EDA tools are becoming available and can be of assistance to the design engineer to help manage these effects. It is expected that there will be a period of maturation necessary for these new tools to evolve and provide results that fully satisfy the user community.

Increased Circuit Speeds

Chips with 1-Ghz clocking speeds are now in design. To achieve clocking speeds of 1-Ghz, the designer may again draw more on structured custom methodologies with heavy emphasis on optimized architectural approaches, such as more use of data path structures, yielding the highest speed possible. Clock source jitter may become a problem, and more attention will be given to global skew optimization.

Managing Design Complexity

For designs incorporating cores, the management of complexity may actually be simplified with a structured-core approach. For example, timing may be verified within the core by the in-company or external core development group, and then globally for the interconnect between cores by the core integrator. However, critical paths may span both and will require special attention.

Designers are finding that tools operating in a robust manner on previous designs break due to capacity limitations. 32-bit UNIX operating systems have a 4-GB memory addressability limit. This addressability limit is being exceeded when full chip processing is done at a low level of abstraction, and when design processes occur at the full chip level. A temporary solution is to decompose the design into smaller blocks, but this is time consuming and an unnecessary waste of time. A solution is discussed later in this paper.

Chips of 1 to 2 million gates require many gigabytes of data storage. Synthesis, simulation and formal verification run times can become prohibitively long. Chips of this complexity present a challenge in data management as teams of designers take responsibility for specific blocks, or design processes. Combined version control software and computer resources for data management are the best solution.

Hardware/Software Co-Design & Verification

When a microprocessor is embedded within a design, new design techniques in hardware and software co-design are being applied. Co-design systems may utilize commercially available instruction set simulators linked to a HDL model for co-simulation. Conventional In-Circuit-Emulators are being superceded with ASIC emulators, PLD prototyping, and software debuggers.

For the final phase of co-verification, developers are applying laboratory instrumentation for probing, real world timing analysis, and source code debugging all correlated and displayed in selected time stamps of real time.

Approaching the Ideal Design Environment
Correct by Design

The ideal design environment would provide robust EDA tools for automatically creating a design meeting function, performance, and reliability in multi-vendor processes. The design would be optimized for least silicon area, specified by the design engineer from chosen levels of abstraction -- circuit, gate, high level language or graphical representation. Is this a pipe dream? Probably, yes. Compare our current methodology to the dominant methodology just a few years ago when ASIC vendors guaranteed fabrication of an ASIC that represented the design as specified with models provided by the ASIC vendor, layout by the vendor, and customer simulation with the back annotated delays. We were closer to the ideal design environment a few years ago than we are now. We have regressed due to unanticipated, or not yet easily solvable design issues. Likewise, EDA solutions are not available when they are needed. More reasonable expectations might be that over time, we will again shorten the development cycle by reducing the current iterative design process, and progress toward "correct by design".

Harnessing the Verification Process

The ideal design environment would include in-process verification, meaning that the design processes would be self-verifying, and that a final verification would be made just as a check before tape-out. The verification process should make suggestions not included with correct-by-design tools for improved manufacturability of the design and only yield identification of occasional errors that became evident when the design is analyzed at the full chip level.

Seamless Tool Processes

Until now, not one EDA supplier appears to provide highly integrated and optimum industry preferred tools for an entire design system. A seamless user design environment with patched "foreign" tools causes user inefficiencies as design time is consumed in transforming data from one tool to another, or when a common display of data is not available from multiple tool processes. While some EDA companies are cautiously taking steps to advance tool interoperability, much remains to allow for seamless integration of mainstream tools. Your CAE support and methodology personnel, or contracted CAE services, often can provide the stitching necessary for tool interoperability, but often are not able to achieve a seamless user efficient solution. Most users will state a preference for optimum functionality in EDA tools over seamless integration. But, they would like both. Coupled to the seamless tool processes is the computing environment itself. A poorly planned computing environment by itself can lead to user inefficiencies. There is an opportunity for design methodology engineers not only to wisely design the design processes, but also to plan and provide an optimum computing environment for design.

Taking Advantage of Hierarchy

Planning the design hierarchy, even with some automation assistance, helps in design visualization and can help in data management. However, Lucent Technologies Microelectronics (1) has studied how chip design hierarchy can be of more help to the designer. They found that the application of hierarchy is encumbered in the design flow from one tool to another. For example, floorplanners need more flexibility in grouping cells as revisions are made in the design. They also found that hierarchy has a high dependence upon a two-dimensional view so important in layout. Improvements are necessary in data representation and linkages from one tool to another.

Powerful Virtual-like Computing Environment

We are coining a new phrase, "virtual-like computing". A user would like instantaneous results from tool processes, and would prefer not to spend time managing job distribution, job queuing, and data management. Advanced design departments are making progress toward reaching a virtual-like computing environment. Solutions come from good methodology, wise computer resource planning, and facilitation with EDA centric computers and networking. We will describe techniques and options available to you to help start you on the path to a powerful virtual-like computing environment.

Optimizing for Highest Design Productivity

Data Management

Not modifying the latest version of your design module to correct the latest design flaw leads to catastrophe. Complex design projects require data management and version control for chip modules such as cores, memory, and at the full chip level. Design responsibility for modules and cores may cross design teams and often span more than one company. Tools and computer systems are available for collaborative team development over LANs and WANs. Data control is also needed at different levels of abstraction of a module and chip. Tools to assist in version management are well worth the investment. A computer server is the best resource for maintaining control of your data. The largest disks are available with servers. Their capacity is needed for the massive amount of data that you need to manage. It also serves as a warehouse of the current master files, and previous file versions if you wish to keep them temporarily.

If your choice is to keep "working" copies on client computers dedicated to individual engineers, the master copy should be updated under version control following pre-planned and documented procedures.

The Right Computer for the Required Tasks

Distributed processing throughout an engineering organization time and again wins as 'the designer's choice'. The cost/performance ratios, instantaneous access, and response time are such that the personal workstation wins for heavily interactive tasks, quick design analysis, personal data management, and electronic communication. Creating a design in an HDL with syntax checking, or graphically, then floorplanning, and proceeding with immediate analysis is most appropriate to accomplish on client computers.

Networking to application and data management servers is recommended for the heavy duty processing. Some organizations may steal 'cycles' from other distributed workstations, or run batch jobs overnight as distributed parallel processing. This may be acceptable in temporary situations, but a design team that wishes to optimize their design process will prefer application servers as the next level of processing. These servers are available in single and many processor models.

Uncapping Capacity Limits

If you notice that you are waiting too long for jobs to complete on your own client workstation when you could be advancing your design, it is time to move up to an application server for those jobs. You will be able to complete your interactive work and run most module level design steps on your client workstation. Tools that may call for an application server are synthesis, formal verification, simulation (big jobs), DRC and Placement and Routing. If you are designing chips and running device level verification and interconnect analysis, those call for an application server.

Designs of only several hundred thousand gates call for a 'big gun' for most jobs run at the full chip level. Regression tests for chips of this size are known to run up to 10 to 12 days, even on a powerful application server. The best solution is to move to either a native code simulator, or to parallel processing if supported by your EDA vendor. A native code Verilog simulator running on a powerful application server can increase your throughput twenty fold when run on the same server as standard Verilog. Be sure to investigate parallel processing computer servers, and check with your EDA suppliers to see if your applications are supported on these big guns. The EDA supplier can provide you with example improvements in throughput for their applications as you add processors.

Interoperability of Computing Tasks

The personal computer has moved up in consideration for some design tasks. Users are satisfied using a PC for average size printed circuit board design, low end to mid-size PLD design, and design entry and simulation of small modules of a chip. The NT operating system running on a high-end Intel, or Intel compatible, microprocessor is purported to be positioned for EDA applications where UNIX on RISC-based workstations and servers have been the choice.

The jury is still out. Decades of UNIX code evolution in providing dependable, robust, high capacity, and networked processing in worldwide R&D organizations still has the warm fuzzy feel, and this is because its use is backed by our own experiences. Most chip design organizations, as reflected by panel members at DesignCon98, believe that there are no compelling reasons to experiment with NT for mission critical IC design tasks. If the application is not that critical and you don't mind re-booting occasionally, perhaps you would choose to bring some Wintel or NT ported products into your computing environment.

This presents the case for interoperability of UNIX and NT based applications in the computing environment for electronic design. Without interoperability, I can not see introducing yet another nuisance into your design flow to slow your design progress. The interoperability solution should include not only UNIX and NT, but also multi-vendor computer support for your computing environment. If your evaluation shows that you can depend upon NT, you will want your computer supplier to offer interoperability support.

Shortest Time to Solution

However you choose to optimize your design environment, the shortest time to your solution is the obvious goal. By this I mean that any noticeable wait time - whether for set-up, compiles, brute force processing, or display of the results, any processing that extends your time to solution. Iterations in your design process will be faster with the most powerful computers, but your preference should be to create the solution with fewer iterations of design process steps. If the EDA technology is not capable of reducing iterations, then a powerful processing solution is your best choice.

We have discussed planting your computer farm with processors chosen so that the application or design processes are matched. There is a place for work-station clients, whether UNIX or NT, a place for application servers, a place for data management servers, and a place for the big gun, parallel processing as illustrated in Figure 1.

Figure 1

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