A Giant Step to Electronic System Design

Cadence Design Systems' release of Cierto Virtual Component Co-Design (VCC) is a giant step forward in electronic design automation (EDA) for system level design. From a chip design perspective the design community has required incremental steps up the ladder of abstraction. We were unsuccessful 'skipping' from gate level to behavioral level design. Register transfer level (RTL) design became the method of choice. Behavioral-level synthesis has only been adopted for niche application. From a system design perspective, there has been extensive use of C-level specification and simulation, but translating system architecture into synthesized hardware and software code has been cumbersome. Instruction-set simulators have been used when applicable. Cierto VCC offers the design community the opportunity to take a giant step to a more automated electronic system design methodology.

Cadence's vision is that there is a market for tools that support electronic system design whether at the highest level of system definition and design, or at the chip level. Cierto VCC may be applied at the system behavioral level, the hardware/software interface level, or to evaluate the opportunities with alternative microprocessor, DSP, or memory cores. High-level languages including C, C++, SDL, the Cadence Cierto SPW may be used to specify the behavior desired. A cycle approximate estimation capability is added to complement cycle accurate instruction-set simulation used in co-verification for helping the designer with co-design decisions with early estimates of processor load and system scheduling prior to implementation. Architecture alternatives may be simulated. For example a real time operating system may be simulated with trial hardware architecture and CPU and/or DSP models. The system performance may be evaluated, bus congestion analyzed, task scheduling determined, and high-level timing with delay models predicted. Finally the communication interface logic is synthesized to Verilog or VHDL at the RTL level and C code generated for the software. For software this export process inserts the calls for the select RTOS and reassembles the drivers and modules as provided for an IP core such as a ARM microprocessor.

Some system architects and designers have used individual tools to accomplish these very same tasks. Cadence with the research contributions of the Felix Initiative has introduced a cohesive system design methodology with supporting novel tools. The methodology is the result of collaboration with customer system architects, software developers, and hardware system and chip designers.

If the Cierto VCC is applied throughout the architecture development and system design process, system design productivity is expected to take a giant step. There can be benefit in applying individual capabilities but that would only be an incremental step from current system design techniques. The challenge that Cadence must overcome with Cierto VCC is that the system architect, the system designer, and hardware and software developers are satisfied that Cierto VCC complements the application of their creative skills with automation to improve the "time to solution". At this level of design, it must improve the definition, architecture development, and early performance evaluation steps. The output from Cierto VCC must present the system solution such that software development, reuse application, and silicon implementation may be completed without nuances or obstacles emanating from the high-level system design process. When product changes are needed, the architecture and design development record must help point developers to where and how such product changes can best be made.

To look forward, the design community needs an analog component to the system design process described. Analogy's Saber simulator (about to become Avant!'s by acquisition) has a system level simulation capability. Antrim's new product, Antrim-MSS, is positioned to automate circuit implementation with analog circuit synthesis. These tools have some of the functionality that system and hardware designers could use to improve both high-level and circuit level design and implementation of analog inclusive systems.

URL: http://www.cadence.com/press_box/na/pr/2000/01_10_00kit.html

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