Chip Design Solutions for Deep Sub-micron Effects - Part I

New electronic design automation (EDA) products are being offered for solving one of the most pressing problems facing chip designers of high-complexity chips, that is timing closure. Some of the new EDA products offer simultaneous analysis of power and signal integrity with timing optimization. They provide the opportunity to shorten the design cycle when the design is to be fabricated in leading edge semiconductor processes.

The chip design problems often referred to as 'Deep Sub-micron Effects' are discussed in my article, "The Search for a Breakthrough in IC Design Productivity" available in the EDA and Computer archives of this site. As described in my previous article we have regressed in the ability to guarantee chip performance and quality of results due to EDA systems not properly accounting for the larger delays in wire interconnect compared to transistor delays and to clock skew, cross talk sensitivities, and power considerations. Add to this the current advancement in semiconductor processes that enable designers to design more logic and memory on a single chip. The data representation of complex chips exceeds the memory capacity of 32bit high-end servers. The "time to solution" has therefore increased as designers were forced to cycle their design through elongated analysis steps from trial cell placement and routing, and use piece meal techniques to complete design steps with 32bit servers.

A capsule summary of products from Cadence Design Systems, Monterey Design Systems, Sapphire Design Automation and Synopsys follows. These companies through a spokesperson have submitted a brief vision statement of how their products address the deep sub-micron design barriers.

Envisia PKS - Cadence Design Systems

Envisia PKS is a physical synthesis system developed with functionality from the acquired Ambit BuildGates synthesis system and Cadence's Silicon Ensemble place and route technology. Cadence has integrated global placement and routing into the synthesis process. They believe that incremental synthesis, placement, and global routing to be the best solution for achieving timing closure in one pass. With PKS this process is constraint driven for both area and timing to achieve the smallest die size and required timing. PKS will guide the user during the synthesis and placement process. PKS incrementally optimizes both the timing and physical views of the design and returns the optimum solution for a given set of constraints. With concurrent optimization, Cadence claims that PKS will return results that correlate within 5% to the finished design (post place and route). Cadence addresses signal integrity and power analysis including IR drop and electro-migration analysis during the detail routing phase with Silicon Ensemble.

High-level floor planning allows for the placement of blocks, pin assignment and chip aspect ratio preference. Data paths may be pre-placed as a fixed block, or be synthesized from either gate or from a RTL description with PKS.

Cadence's announced customers using Envisia PKS include NEC, Hewlett-Packard and IBM.

"It is best to attack the timing closure problem at the root cause by integrating accurate timing capability within proven high capacity synthesis and proven placement and routing technology." Mike Carrell, Marketing Manager, Envisia PKS

Dolphin - Monterey Design Systems

Monterey Design Systems' Dolphin is an integrated physical design system developed for complex system-on-chip design. Dolphin simultaneously explores the physical and electrical design spaces, including placement, routing, timing, logic optimization, clock, power, and cross talk. The user specifies constraints for timing and area. Logic is optimized and routing congestion minimized for routeability and area reduction. A fixed die size may be specified and Dolphin will estimate during the partitioning phase whether other constraints such as timing, power and signal integrity can be maintained. The product includes a static timing analysis tool, a detailed global router and a detail router.

The integrated static timing analysis tool runs at every placement step. At the same time, the inherent technology evaluates crosstalk, IR drop, noise and electromigration that could be caused by placement. Net extraction occurs along with placement. 3-D RC extraction occurs on selected critical paths. An n-layer shape-based gridless router may conform to a grid when needed. The router creates variable wire widths to optimize timing delays and has built-in capability to avoid cross talk and antenna issues.

Current customers are Fujitsu and Creative Technologies. Other companies are in an evaluation phase of the product. At this writing the product is supported on 64bit single and multiprocessor workstations and servers from Hewlett-Packard and on 32bit and 64bit single processor workstations and servers from Sun Microsystems.

"Complete design closure including timing closure is critical to the success with deep submicron designs. A global simultaneous optimization approach allows high quality silicon to be achieved in one pass, eliminating time consuming and costly iterations." Tom Quan, Director of Marketing, Monterey Design Systems

FormIT, NoiseIT, PowerIT - Sapphire Design Automation

Sapphire's tool names are self-descriptive of the tool applications. The approach is to perform a detailed timing, noise and power analyses, then optimize in parallel with detailed placement. Routing directives are generated to influence the router for timing critical and noise sensitive nets. The tools are applied after synthesis and provide the placement data directly to Cadence's Gate Ensemble or Avant!'s Apollo routing products. Their experience is that the silicon area is increased a maximum of 1 or 2% and with their logic optimization capability the silicon area often may become smaller with application of the electrical optimization tools.

Sapphire's announced customers are NeoMagic and Sandcraft. A few other companies have purchased the tools and several others are in the evaluation mode.

"The optimum solution for solving the deep submicron effects in chip design is to integrate electrical analysis, circuit optimization and detailed placement". Dhiraj Sogani, Director of Marketing, Sapphire Design Automation

Physical Compiler - Synopsys, Inc.

Building upon its success with synthesis, Synopsys has just released the Physical Compiler. As may be expected the Synopsys solution emphasizes consideration of physical layout parameters during the front-end design process. Physical Compiler is the latest component of the Synopsys Physical Synthesis solution.

In the Synopsys flow, Chip Architect is applied as a design planner prior to RTL specification. This step includes chip-level planning, block placement, pin assignment, and constraint budgeting. The FlexRoute top-level router may be used for final, detailed routing of the top level of the chip.

After the design planning phase, Physical Compiler is employed to implement blocks. Physical Compiler combines Synopsys' own placement engine with RTL synthesis to produce both a netlist and final cell placement. By adding cell placement to synthesis, Physical Compiler has an accurate view of timing and is able to achieve timing using not only logical optimization, but also cell placement optimization.

After the design meets timing at the placement level, the netlist, floorplan, and cell placement is transferred to either Cadence's Silicon Ensemble or Avant!'s Apollo detailed router for final chip implementation. Constraints for physical synthesis with this solution may be area optimization preference or timing optimization preference, or both area and timing. Power optimization and test insertion is available with the Physical Compiler product.

Synopsys has announced its intention to offer a standard cell router in the future.

Physical Compiler customers include STMicroelectronics, Matrox Electronic Systems, NEC and NVIDIA; other companies are in evaluation of Physical Compiler.

"With the addition of Physical Compiler to the Physical Synthesis solution, Synopsys now offers designers the most advanced timing closure solution that leverages their vast experience with Design Compiler. By unifying synthesis and placement, we have solved the most important problem for timing closure - the separation of logical and physical design" Tom Ferry, Director of Marketing, Physical Synthesis Business Unit, Synopsys, Inc.

This sampling of new products indicates that design engineers who choose to apply these tools will also be adopting alternative methodologies. Compared to the recent "trial and error' method to achieve timing closure the design community will be willing to adopt a new methodology.

Some suppliers believe signal integrity analysis and solutions go hand in hand with timing optimization. Likewise the wire location and size should be controlled with data from this analysis. Most suppliers who have strengths in these areas do not have there own logic synthesis products even though they perform logic optimization. This means that the synthesis net list and the post analysis net list will be different. When LVS is run, you have a choice of net lists. Which will you choose? When a design change is to be made, or the design is to be reused, which net list should serve as your master design?

Those suppliers that have design synthesis and physical synthesis would like their customers to set their sites on long term use of physical synthesis. While they are committed to enhancing and marketing their current design synthesis products for the foreseeable future, I believe that they would like the economies of supporting one synthesis product. For this to occur, the large installed base of synthesis users will need to make major investments in the higher priced physical synthesis tools, or the suppliers will need to offer a more attractive upgrade plan. Those designers who are not yet pushing the envelope by designing with the most advanced semiconductor libraries may delay such an upgrade investment for some time.

The author is pleased that EDA companies are making R&D investments to provide solutions for much needed problems. It is expected that the new tools will provide valuable benefits to the design community. Early users of the tools will help define needed enhancements both in algorithms and methodology. Its just that those suppliers with advanced technology in solving timing, signal integrity, power containment would like to integrate their solutions better with the leading synthesis and router products. And the companies having the leading synthesis or routing products would like to have the most advanced technology in electrical analysis and optimization. We can expect the merger and acquisition interest to continue. Or the market for these products will become crowded with many suppliers of full-featured products.

More on this in a forthcoming Part II on this topic.

URLs for Web Sites

www.cadence.com
www.montereydesign.com
www.sdai.com
www.synopsys.com

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