Electronics Design Checklist

This checklist is for electronics designers and technicians who would like to share experiences and create a detailed checklist which the individual designer can pare down to meet his or her specific needs. There are many details that go into making a first-run design success and this checklist helps prevent Murphy's gremlins from marring an otherwise healthy design.

How do you use this checklist?

1. Make a copy of the list on your computer. Edit the rules to conform to your company's practices and delete the rules that do not apply to your work.

2. Discuss the checklist with others you work with, adding items from their experience. For maximum benefit, get their commitment to use it, too.

3. Make the checklist part of your design review and design release procedures. Do not release a product for prototyping or manufacturing until each checklist item has been verified.

4. Keep the original checklist for each release or revision so you can close the loop on the process, adding some items later if needed. For each design error that occurs, add an item to the list.

5. Contribute your suggestions for additions or changes so others can benefit from your experience. Mail suggestions and feedback to EE Expert Hank Wallace.

1. Electronic and Schematics
1. all unused inputs terminated
2. race conditions checked
3. Darlington outputs (1.2v low) driving logic inputs
4. mating connectors on different assemblies checked for same pinout
5. all outside world I/O lines filtered for RFI
6. all outside world I/O lines protected against static discharge
7. bypass cap for each IC
8. voltage ratings of components checked
9. ensure 3.3 volt parts are 5 volt tolerant where they interface
10. verify power sequencing requirements on 5 volt and 3.3 volt rails
11. each IC has predictable or controlled power-up state
12. file name on each sheet
13. dot on each connection
14. minimum number of characters in values
15. consistent character size for readability
16. schematics printed at a readable scale
17. all components have reference designators and values
18. special PCB or parts list information entered for each component, if required
19. polarized components checked
20. electrolytic and tantalum capacitors checked for no reverse voltage
21. power and ground pins listed for each component with hidden power pins
22. check hidden power and ground connections
23. title block completed for each sheet
24. ground made first and breaks last for hot pluggability
25. pullups on all open collector outputs
26. separate pullup/pulldown resistors on all mode pins to allow modes to be changed if needed
27. sufficient power rails for analog circuits
28. LM324 and LM358 outputs loaded to prevent crossover distortion
29. amplifiers checked for stability
30. oscillators checked for reliable startup
31. consider signal rate-of-rise and fall for noise radiation
32. check for input voltages applied with power off and CMOS latchup possibilities
33. reset circuit design reliable, both glitch-free and consistent; tested with fast and slow power supply rise and fall time
34. check reset behavior if power cycles before the circuit is fully operational
35. for synchronous resets be sure the circuit can withstand unknown outputs until the clock starts
36. check all resets for possible reset loops, especially for designs that are hot swap capable
37. separate analog signals from noisy or digital signals
38. ability to disable watchdog timer for testing and diagnostics and emulation
39. sufficient capacitance on low dropout voltage regulators
40. setup, hold, access times for data and address busses
41. capacitance and fan out limits checked for busses
42. check the data sheet fine print and apnotes for weird IC behaviors
43. determine effect of losing each of multiple grounds on a connector
44. automotive powered devices must withstand 60 to 100 volt surges
45. check maximum power dissipation at worst-case operating temperatures
46. check time delays and slew rates of opamps used as comparators
47. check opamp input over-drive response for unintended output inversion
48. check common mode input voltages on opamps
49. check for voltage transients and high voltages on FET gates
50. check failure modes and effects of failed power semiconductors
51. estimate total worst case power supply current
52. check pin numbers of all custom-generated parts
53. pinout may vary between DIP and various SMD packages; library parts may not match the intended package
54. for buses, ensure bus order matches device order
55. ensure resistors are operating within their specified power range plus safety factor
56. resistor power ratings derated for elevated ambient temperatures
57. electrolytic/tantalum capacitor temperature/voltage derating sufficient for MTBF
58. check for low impedance sources driving tantalum caps which can cause premature failure
59. avoid reverse base-emitter current/voltage on bipolar transistors
60. check PLD pinouts each time a PLD is recompiled
61. preferred component reference designators
1. R fixed resistor
2. RN resistor network
3. RV variable resistor
4. C capacitor (network, fixed or variable)
5. L inductor
6. Q transistor, FET, SCR, TRIAC
7. D,CR diode, rectifier, Zener, varicap, LED
8. DL multisegment display (any type)
9. VR,Q,IC voltage regulator
10. U,IC integrated circuit
11. J socket, jack (female) OR the half that is stationary
12. P plug (male) OR the half that is attched to a cable/wire
13. JP jumper (pins, trace, or wire)
14. Y,X crystal
15. M modular subassembly, daughter board
16. S mechanical switch
17. F fuse
18. FL filter
19. T transformer
20. KB keyboard
21. B,BT battery
2. PCB Design
1. hole dia on drawing are finished sizes, after plating
2. finished hole sizes are >=10 mils larger than lead, or larger spec dictated by automatic insertion gear
3. silkscreen legend text weight >=10 mils
4. pads >=15 mils larger than finished hole sizes
5. place thruhole components on 50 mil grid
6. no silkscreen legend text over vias (if vias not soldermasked) or holes
7. soldermask does or does not cover vias
8. all legend text reads in one or two directions
9. components labeled left-right, top-bottom
10. company logo in silkscreen legend
11. company logo in foil
12. copyright notice on PCB
13. date code on PCB
14. PCB part number and layer number on each layer in copper
15. assembly part number on PCB
16. all polarized components point same way
17. components >=0.2" from edge of PCB
18. ground planes where possible
19. test pad or test via on every net to allow in circuit test
20. for in-circuit test, no logic pins connected directly to power or ground
21. test point on all unused outputs for use in debug
22. test pads 200 mils from edge of board
23. mounting holes electrically isolated or not
24. mounting holes with or without islands
25. proper mounting hole clearance for hardware
26. all polarized components checked
27. no acute inside angles in foil
28. traces >= 20 mils from edge of PCB
29. PCB revision on silkscreen legend
30. assembly revision blank on silkscreen legend
31. serial number blank on silkscreen legend
32. soldermask swell checked
33. thru hole drill tolerance noted
34. thru hole soldermask tolerance noted
35. thru hole route tolerance noted
36. thru hole silkscreen legend tolerance noted
37. drill legend shows all symbols and sizes
38. mounting holes matched 1:1 with mating parts
39. automated netlist check
40. manual netlist check
41. check netlist for nodes with only one connection
42. all nets have meaningful names with modifiers for signal polarity, differential signals, busses
43. net names case insensitive, alphanumeric, name length compatible with other tools
44. beware a net named NC
45. verify that nodes in a netlist with more than N connections are valid
46. CAD design rule check
47. drill origin is a tooling hole
48. checkplots sent with disk based photoplot files
49. NC drill and photoplot file language format noted
50. tools on drill plot and NC drill file cross checked
51. soldermask over bare copper noted if needed
52. PCB thickness, material, copper weight noted
53. trace and space geometry noted
54. printed drill report sent with checkplots
55. printed aperture table sent with checkplots
56. photoplot files checked in file viewer
57. test coupon on PCB containing minimum geometry features
58. trace width sufficient for current carried
59. minimum component body spacing
60. SMD pad shapes checked
61. visual references for automated assembly
62. tooling holes for automated assembly
63. tooling and mounting holes have internal plane clearance to avoid multilayer shorts
64. sufficient clearance for high voltage traces
65. component and trace keepout areas observed
66. high frequency circuitry precautions observed
67. thermal reliefs for internal power layers
68. solder paste mask openings are proper size
69. blind and buried vias allowed on multilayer PCB
70. PCB layout panelized correctly
71. panelized PCB fits test and manufacturing equipment
72. breaking or cutting apart panelized PCBs after loading can stress/crack SMD parts near the break points; place parts away from stress areas
73. sufficient clearance for socketed ICs
74. SMD component orientation arbitrary or consistent
75. ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board
76. clearance for IC extraction tools
77. clearance for emulator adapter
78. clearance for sockets for ICs during proto phase
79. standoffs on power resistors or other hot components
80. digital and analog signal commons joined at only one point
81. EMI and RFI filtering as close as possible to exit and entry points in shielded areas
82. layout PCB so that any rework or repair of a component does not require removal of other components
83. extra connector and IC pins accessible on prototype boards, just in case
84. check all power and ground connections to ICs
85. provide ground test points, accessible and sized for scope ground clip
86. potentiometers should increase controlled quantity clockwise
87. check hole diameters for odd components: rectangular pins, spring pins
88. check the orientation of all connectors using actual connector/cable
89. bypass capacitors located close to IC power pins
90. all silkscreen text located to be readable when the board is populated
91. all ICs have pin one clearly marked, visible even when chip is installed
92. high pin count ICs and connectors have corner pins numbered for ease of location
93. silk screen tick marks for every 5th or 10th pin on high pin count ICs and connectors
94. verify that all series terminators are located near the source
95. place I/O drivers near where their signals leave the board
96. high frequency crystal cases should be flush to the PCB and grounded
97. check for traces running under noisy or sensitive components
98. check IC pin count on layout vs schematic
99. no vias under metal-film resistors and similar poorly insulated parts
100. check for traces which may be susceptible to solder bridging
101. maximize distances between features where possible
102. check for dead-end traces
103. check for PWR not shorted to GND
104. ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed
105. provide multiple vias for high current and/or low impedance traces
106. ensure component fiducials are present on fine pitch parts, minimum 2 per component
107. ensure global board fiducials are present, minimum 3 per board in opposing corners
108. if layout is panelized, ensure panel fiducials are present, minimum 3 per panel in opposing corners
3. PCB Assemblies
1. miscellaneous parts on bill of materials and assembly notes for same: hardware, heat sinks, heat sink compound or composite insulators, IC sockets, consumables
2. assembly notes for all special operations
3. conformal coating
4. special static handling precautions required during assembly and test
4. Wired Assemblies
1. wire gauge checked for compatibility with each termination
2. cable ties or lacing cord shown where needed
3. length and color of each wire indicated
4. check voltage drop at maximum current with specified gauge and length for entire current path (eg. power and ground)
5. notes about application of wire terminations (technique, heat shrink tubing, amount of solder, crimp force, tools, etc.)
5. Parts Lists
1. each component has quantity, reference designator and description
2. list qualified part numbers for special devices
3. suggested and alternate manufacturer(s) listed
4. object/binary code and method/programmer specified for each programmable device
5. price and availability checked for each component
6. Mechanical Drawings
1. standard title block and border used
2. no dimensions on the material
3. every feature must have X and Y dimension, along with radius, diameter, etc.
4. every hole must be checked for alignment with mating hole(s) in other parts
5. check every hole diameter
6. tolerance for sheet metal feature position noted
7. tolerance for sheet metal hole size noted
8. specify material
9. specify finish
10. specify units
11. specify debur or brush
12. details for special operations
13. file name on each sheet
14. CAD layers shown on drawing
15. all hardware specified and listed on parts list
16. screw lengths checked; extra thread required for fasteners (nut, lockwasher, washer)
17. hole diameters checked for each screw
18. tapped hole thread details indicated
7. Software
1. each version archived for future reference
2. loops checked for terminating conditions
3. communications timeouts checked
4. all branches tested
5. revision history noted for all changes
6. CPU utilization measured
7. interrupt response time measured
8. interrupt execution time measured
9. naming conventions consistent and relevant to humans
10. adherence to coding style standards
11. power-up, power-down considerations
12. unused vectors trapped to restart or damage control routine
13. unused ROM space loaded with trap or restart instructions
14. warm and cold reset differences
15. nonvolatile memory corruption possibilities checked during power-up, power-down, and program-gone-wild conditions
16. design notes within or separate from code
17. check for FIFO and buffer overruns
18. check critical timer driver code
19. check for odd address usage on 16/32 bit micros, especially an odd stack pointer
20. use a LINT utility on C programs to find subtle problems
21. program's data structures contain version numbers to detect program version upgrades and translate the structures' formats
8. Testability
1. test points on PCBs for critical circuits, hard to reach nets
2. test pads for in-circuit or bed-of-nails functional testing
3. test pads on a regular grid
4. test procedure written for each test phase
5. special test arrangements and connectors for testing
9. Maintainability
1. easy disassembly and reassembly
2. fuses accessible and labeled
3. self test mode
4. spare parts available
5. status LEDs on PCB
6. event logging of exceptional conditions
7. vibration tolerance of entire assembly and individual modules
8. surge current magnitude through semiconductors within rating
9. thermal cycling excursions internal to components and assemblies within acceptable limits
10. capacitors mounted below or away from heat-dissipating devices such as transformers
11. resistance and tolerance of entire product to static discharge via any path
10. Safety
1. fuse and circuit breaker size and characteristics
2. fuse sizes marked near fuse holder
3. room to remove fuse without damaging other components
4. spare fuse storage
5. shock hazards
6. radiated energy warnings and shields
7. applicable standards checked
8. protection against liquids and foreign objects
11. Documentation
1. end-user instructions: unpacking, how to use, warranty, service, troubleshooting
2. service manual: troubleshooting procedures, parts lists, helpline info
3. design notes: why were significant design decisions made the way they were
4. other info that may be lost if designers depart the organization

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