STD Bus Can Be Enhanced by Adding a Power Bus
by Walt Morrey

The STD Bus has been around for a long time—ANSI/IEEE Std 961 was published in 1987 and is still extremely useful for embedded systems. The initial spec allowed for a 16-bit address bus, 8-bit data, 8-bit I/O address space, with a pin for I/O expansion (IOEXP). This is fine for most embedded systems, especially since CPU boards alone can now have all the computing power and memory required for even the most complex applications.

One limitation of the STD Bus is that it has limited power control capabilities. Users of the STD Bus will add external PCBs to control power, stepper motor drivers, etc.

I have developed an STD Bus backplane with 8 STD Bus slots and 4 additional power card slots. The backplane has an overall size of 5.25" × 12.00". The cards have the same form factor as the STD Bus cards, but have only 44 pins. Power control PCBs require a limited control data rate. These boards accept serial input data with a separate board select. The data are serialized in a Xilinx XC9572 IC socketed on the backplane. The XC9572 also generates the 4 board-select controls. The XC9572 decodes 8 addresses in the I/O address space of the STD Bus (normally E0–E7). This backplane allows for the generation of all the STD Bus power lines from a single +24 V DC power supply. It also provides filtered +24 V power to up to 4 loads (fans, stepper motors, etc.). It is wired for one of the power cards to include a relay to switch the main +24 V to a switched 24 V power line and a D/A converter to control an external auxiliary power supply. In addition, interlock headers are provided for operator protection if the auxiliary power supply drives something potentially hazardous (like an X-ray tube). Headers are also provided to allow easy connection of standard off-the shelf power supplies.

The XC9572 design is shown below.

Data I/O Bus

Address and Control Inputs

D7–D0, A7–A0, RD-, WR-, CLK, RST-, IOEXP, and IORQ- come from the STD Bus.

CLK is the master system clock, available on the STD Bus, and is typically 3 MHz. CLK sets the serial data rate to the power cards—2 CLK periods occur for 1 serial bit interval.

SDO is the serial data returned from the power cards. Generally, only one power card is allowed to return data at a time.

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Address Decoder and Power Board Enable

When A7–A0 is between 0xE7 and 0xE0, IORQ- is low, and IOEXP is also low, RD or WR access the XC9572.

When writing, if A7–A0 is between 0xE3 and 0xE0, the appropriate board select line is set to 0. If A7–A0 is between 0xE7 and 0xE1, the appropriate board select line is set to 1. At power-up, all board select lines are set to 1. This way, each power board can have as many bytes of data input or output as needed.

Any read just puts the outputs of the shift register on the STD Bus.

SRLDEN goes to 1 to load all 8 bits of the shift register asynchronously on any write.

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Divide-by-24 Free-Running Counter

The STD Bus master clock, CLK, is divided by 24 to generate a free-running output clock. If CLK is 3.00 MHz, the free-running clock will be 125 kHz. This can be used on the power cards to synchronize pulse-width modulators, switching regulators, or other control circuitry. CNT4–CNT0 count from 0 to 23, with CNT23 going to 1 when CNT = 23.

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Serial Clock Generator

When SRLDEN goes to 0 (the data are stable in the shift register), a latch is set. The next time CNT4–CNT0 goes to 23, and SREN is set to 1, which clears the latch and enables CNT0- to drive SCK to the power cards.

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Shift Register — Bits 0–3

The shift register is loaded asynchronously whenever SRLDEN is 1. Data are shifted in and out whenever SREN is 1.

Normal Operation To Access Power Board 0

The first 8 bits of the data for Power Board 0 are written to I/O address 0xE0, which sets SEN0 to 0, enabling Power Board 0. The next time CNT4–CNT0 goes to 23, SREN is set to 1, and 8 clocks are generated to SCK. This shifts out the 8 data bits to SDI and shifts 8 data bits in from SDO from Power Board 0. The shift process is complete within 40 CLK cycles maximum.
The STD Bus controller reads I/O address 0xE0 to get the first byte of data from Power Board 0.
The next 8 bits of data for Power Board 0 are written to I/O address 0xE0, and the process continues.
The next 8 bits from Power Board 0 are read at I/O address 0xE0.
Steps (3) and (4) are repeated as necessary.
When all of the data for Power Board 0 have been written and read, the STD Bus controller writes to I/O address 0xE4 to disable Power Board 0 explicitly, which also generates a serial data stream and clock. This serial data stream can be used an a Listen-Only Master Command to all the power boards, if desired, for instance to trigger more than one board to synchronize operations.

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