Today's Feature

Chip Designers Move Back from Bleeding Edge by Ron Wilson, EET
The Hot Chips conference, which opens at Stanford University, has long been the showcase for processors that hit blistering speeds by way of advanced architecture, bleeding-edge processes, and full-custom design. But this year two papers will offer a different perspective, touting unconventional semi-custom design methodologies that wring the same kind of speed from familiar architectures and ordinary processes.

PalmChip Bus Patent Threatens Most SoCs by Ron Wilson, EET
A patent granted to PalmChip Corp. covers the techniques used to implement on-chip CPU bus structures in nearly all modern system-on-chip (SoC) designs, the company said. CPU or system-interconnect intellectual-property vendors and most SoC design teams may be infringing the new patent, PalmChip warned.

Phase Noise and Jitter -- A Primer for Digital Designers
Hot Chips Conference Reflects a Changing Industry
Managing Loss in High-Speed PCBs
Jury Still Out for EDA Industry on Structured ASICs
EDA Quality Remains Elusive Goal
High-k Oxides Knock at Metal Gate
A Midyear Look at EDA

Engineers List Turn-Ons, Turn-Offs by Margaret Quan, EE Times
EE Times and marketing communications firm McClenahan Bruer Communications (Portland, Ore.) commissioned an Internet survey to put a human face on the profession. Respondents were asked about their careers, families, leisure activities, social attitudes and personal preferences. The results paint a picture of a "typical" engineer who both validates the stereotype as well as defies generalization

Today's Feature : Archive

Product Reviews

IBM Pushes PowerPC Licensing
Product Reviews : Archive

Today's Features

Cadence Introduces Incisive Verification Platform (Product of the Week)
The heart of Cadence's unified Incisive top-down verification methodology is the transaction-level-based Functional Virtual Prototype (FVP). According to the company, the creation of transaction models takes a fraction of the time required for RTL descriptions, and the transaction models run about 100 times faster. In fact, the claim is made that the Incisive system and methodology can reduce total verification effort and time by a factor of two—a truly significant reduction in project cost.

Product Reviews

Cadence Introduces Incisive Verification Platform (Product of the Week)
OpenAccess and Synopsys Working Together
IBM Pushes PowerPC Licensing

More Product Reviews

Tech Notes

RTL Handoff by Reed Packer, AMI Semiconductor, Inc.

More Tech Notes

Application Notes

Formal Verification of Equivalence in DSM Design by Roger Hughes, Mentor Graphics

More Application Notes

News

Synplicity Enhances Prototyping Tool
MMIC Design Flow from Agilent
Mentor Unveils PCI Express Controller
Rambus Describes Redwood
ARM Works With Canesta
Cadence First Encounter Selected by TI
Synopsys Announces IP for PCI Express
Lightspeed Uses Sequence for Signal Integrity
ARM and Emuzed Team on Enhanced Functionality
Silterra Standardizes on Mentor's Calibre
Circuit Semantics Joins Synopsys in-Sync Program
Synopsys Adds AMBA Compliance Tool
AMD Selects Atrenta's SpyGlass
Ansoft Announces SIMPLORER
Agere and Accelerant Deliver Technology
InnoLogic Tools Validate Models for ST
Toshiba Selects CoWare
Mentor Calibre Files Available for 90 nm at UMC
Chartered Details Strategy
Verplex Equivalence Checking For Embedded Memories
Monterey Design Deployed TeraChip
Accelerated Technology and MCCI Announce USB Support
ARM Launches AMBA Compliance Program

ASIC News Archive

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