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Design-for-Test has Multiple Dimensions, Experts Say

By Ron Wilson, EE Times

Papers presented at the production test session at Semicon West surveyed the increasing problems that technology integration is causing for the test world. They concluded that chip designers who are asking for higher densities, more complex interconnect stacks, GHz serial I/O and embedded Flash memory are going to have to shoulder some of the responsibility for the test cost of their creations.

Virtually every market for ICs is seeing unprecedented cost pressure. With design and fab costs relatively inflexible, much of that pressure is landing on test designers, according to the presenters here. There is limited flexibility, as a cost-containment program outlined by Saeed Shakeri, vice president of test operations at Advanced interconnect Technologies, showed. Shakeri's figures indicated that ATE equipment cost is rapidly dwarfing labor cost in the test equation.

This is having a number of effects. One is to call into question the use of test floors in developing countries, where labor costs are low, but technical flexibility limited. Another is an increased focus on where every second is going once a die lands on the test head.

Several speakers, in various contexts, pointed to the same techniques for reducing test time. Primary among them were multisite and concurrent testing. In multisite approaches, the tester probes several difference sites on the die at the same time, and conducts independent tests at each site simultaneously.

In other concurrent approaches, the test program may use a combination of multisite probing and built-in self-test to run a number of tests at once.

In effect, these approaches treat each functional block in an SoC as a separate chip, and attempt to test the blocks as close to all at the same time as possible. The limitation, according to Don Blair, principal consultant for Agilent Technologies, is usually access. For multisite probing to be effective, designers must have planned for it by providing landings for the probes on all the sites to be independently probed. For concurrency to work, there must be sufficient access to internal blocks from the external pins to run several blocks at once.

Shakeri, in his concluding paper, called for test engineers to be involved in the design from the beginning, and for the design team to understand the cost implications of test strategies and the capabilities of the test equipment. He said decisions on ATE platforms should be made early in the chip-design cycle, and should inform design for test decisions from there onward.

Tom Napier, director of test engineering services at NPTest, zeroed in on the problem of testing high-performance serializer-deserializer (SerDes) blocks embedded in an SoC. Not only are the high-speed differential serial inputs and outputs from these blocks a challenge, Napier said, but the blocks had become so fast that source-synchronous probing was often necessary to connect to the parallel ports on the fastest SerDes blocks.

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