SRAMs MRAMs

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New Products

Hitachi releases 9/18-Mbit zero bus latency (ZBL) SRAMs for communications applications
Hitachi, Ltd. (TSE: 6501) announced a line of Zero Bus Latency (ZBL) SRAMs as synchronous SRAMs for communications equipment such as routers and switches, and the upcoming release of a total of eight series comprising the 9-Mbit HM66WP18512/3 and HM66WP36256/7 Series, and the 18-Mbit HM66WP18100/1 and HM66WP36512/3 Series. (ChipCenter: WebScan)
SST unveils industry's first 16 Mbit flash/8 Mbit SRAM combo memory device
Previously, designers requiring 8 Mbits of SRAM in a combination memory device were limited to solutions paired with 32 Mbits of flash memory. With the new SST34HF1681 ComboMemory device, designers of low-cost portable applications get the ideal amount of SRAM they need without incurring the costs of additional flash memory. Also, due to the superior features of SST's SuperFlash technology, the new product has the industry's lowest energy consumption of any combination memory device. (ChipCenter: WebScan)
Toshiba develops the world�s smallest stacked multi-chip package currently available
TAEC introduced two four-chip NOR flash and SRAM memory devices, each housed in the smallest multi-chip package (MCP) currently available. The new MCP devices, measuring 10 millimeters (mm) long and 7mm wide, combine 8 megabits (Mb) of Static Random Access Memory (SRAM) and 32Mb Pseudo SRAM (PSRAM) with two 64Mb NOR flash memory chips, increasing overall functionality while reducing board space by 30 percent, as compared to Toshiba�s current MCP offering, which measures 9mm x 12mm. (ChipCenter: WebScan)

News

- New - Cypress, NVE ink technology exchange pact
As part of the agreement, each company will gain access to the other's magnetic random-access memory (MRAM) IP. Cypress will also work with NVE in defending its IP rights under certain circumstances. Cypress has also signed on to manufacture wafers for NVE. Cypress has invested $6.2 million in NVE in exchange for about 3.4 million shares of common stock. The San Jose-based company also has the option to buy up to 2 million additional shares for $3 per share. (e-inSITE)
NEC ships QDR II/DDR II family of high-speed SRAM products
NEC Corp. (NASDAQ: NIPNY) and its wholly owned subsidiary in the US, NEC Electronics Inc., announced the availability of their Quad Data Rate (QDRTM) II and Double Data Rate (DDR) II family of static random access memory (SRAM) products. These products are fully compliant with the second-generation of high-performance QDR and DDR communication memory standards for network switches, routers and other communications applications. (ChipCenter: WebScan)
MoSys and TSMC extend collaboration agreement to 90-nanometer-based 1T-SRAM
MoSys has already taped-out its 1T-SRAM and 1T-SRAM-R(TM) macros optimized for TSMC's 90nm technology. At 0.61u2 (1T-SRAM) and 0.52u2 (1T-SRAM-R), the cells are about half the size of the smallest announced 90nm SRAM cell. This small cell size enables early availability of 1T-SRAM memory designs with densities of 1.1mm2 per megabit. (e-inSITE)
TSMC teams with government on MRAM development
TSMC is the first foundry to signal its intention to integrate the experimental technology into a bulk CMOS process. The company will join with a government research body, the Electronics Research and Service Organization (ERSO), to develop core MRAM technology, including basic cell structure and deposition and etch processes for magnetic thin films. (Electronic Buyers' News)
JEDEC approves QDRII family of high-speed SRAM products
These QDRII/DDRII SRAM specifications set the second-generation, high-performance communications memory standard for network switches, routers, and other communications applications. JEDEC�s approval of the QDRII/DDRII architectures validates customer recognition that these devices constitute an industry standard for high-speed networking SRAM. (ChipCenter: WebScan)
Fujitsu, NEC and Toshiba agree on common specifications for next-generation pseudo SRAM user interface for mobile applications
Each of the three companies will independently manufacture and market PSRAM products based on the common specifications, with product introduction expected to begin in the second half of fiscal 2002. Because the new specifications standardize the packaging and pin layout for the PSRAM, customers will benefit from a uniform design format, eliminating the need to customize designs for each product. (ChipCenter: WebScan)
Intel builds world's first one square micron SRAM cell- first silicon on Intel's 90-nanometer process technology
These cells, the building blocks of memory chips, were built as part of fully functional SRAM devices manufactured using Intel's next-generation 90-nanometer (nm) process technology. The achievement is a milestone toward implementing the new process for production in 2003. (ChipCenter: WebScan)

Resources

ChipCenter Reference Library
This is your access point for lots of good information covering applications, design tools, consultants, intellectual property, trade shows and standards.
Standards Watch
Here is your access point to the standards world.

Georgia Ann Beyersdorfer, Memory Technology consulting editor, has currently completed Suffolk University with a Bachelor of Science in Electrical Engineering.
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