The manufacturer says . . .

ChipCenter's Jon Gabay says . . .

SUNNYVALE, Calif.--Feb. 24, 2003--SST (Silicon Storage Technology, Inc., NASDAQ: SSTI), a leader in flash-memory technology, introduced the SST39VF320, the 32-Mbit extension of its successful Multi-Purpose Flash (MPF®) product family. The SST39VF320 is based on SST's 0.18 µm self-aligned SuperFlash process technology. Leveraging the inherent performance benefits of the SuperFlash technology, the 0.18 µm SST39VF320 MPF product boasts typical chip-erase performance of 1,000 times faster than competing 32-Mbit flash alternatives. In addition, the SST39VF320 offers the industry's smallest TFBGA package (6 mm × 8 mm) for 32-Mbit NOR flash. "By allowing customers to update their code and data much faster, whether during the manufacturing stage or in-system, the SST39VF320 offers a performance leap over conventional flash devices, and can also be a cost-effective alternative for multi-bank flash devices," said Jason Feinsmith, business director, Standard Memory Product Group at SST. "In addition, we paired up the SST39VF320 device with our 6 mm × 8 mm TFBGA package to offer the ideal performance and smallest form factor for portable applications." With chip-erase times 1,000 times faster than conventional flash, SST's customers can erase their flash devices during manufacturing in 40 ms instead of the one or more minutes typical with most flash alternatives. This can save customers time and money, and remove bottlenecks in manufacturing. As for in-system programming, individual sectors can be erased 50 to 100 times faster than conventional flash, thereby reducing power consumption and providing a better end-user experience. The SST39VF320 is ideal for applications such as digital cameras, DVD players, DVD recorders, PDAs, MP3 players, digital TVs, printers, DSL equipment, and networking devices. The new 32-Mbit SST39VF320 represents the first device in SST's 0.18 µm self-aligned SuperFlash technology platform. SST's self-aligned memory cell is novel in the flash industry, and achieves a smaller cell size than in previous SST technologies. SST is simultaneously bringing up three leading foundries, TSMC, Samsung, and Vanguard, to support its 0.18 µm self-aligned SuperFlash technology. "The combination of self-aligned memory cell and 0.18 µm technology brings unprecedented density scalability to our SuperFlash technology," said Bing Yeh, CEO of SST. "These breakthroughs set the stage for SST to expand into higher density products in the near future, while SST also maintains its industry leadership position and firm commitment to the lower density flash business." The 0.18 µm self-aligned SuperFlash technology brings all the benefits, such as superior reliability, low-power operation, small sector size, fast erase time, and logic compatibility to a smaller process geometry, enabling SST to bring forth high-quality products such as the 32-Mbit MPF product. Pricing and Availability SST has been sampling the SST39VF320 since Q4 2002. Production is planned for early Q3 2003. Pricing is $4.55 in 10k unit quantities. Key Features of the SST39VF320 32-Mbit Self-Aligned MPF Product Single-voltage read and write operations: 2.7–3.6 V Low power consumption: active current 9 mA (typ.), and standby current3 µA (typ.) Fast programming: 7 µs per word (typ.) Fast erase times: 18 ms per 2Kword Sector (typ.); 18 ms per 32Kword block (typical); and 50 ms per chip (max.) Fast read access time: 70 and 90 ns Small uniform sector size: 4K per sector Data retention quality: 100 years data retention CMOS I/O compatibility JEDEC standard command sets and pinouts Available in two packages: 48-lead TSOP (12 mm × 20 mm) and 48-ball TFBGA (6 mm × 8 mm × 1.1 mm) About SuperFlash Technology SST's SuperFlash technology is a NOR type, split-gate cell architecture, which uses a reliable thick-oxide process with fewer manufacturing steps, resulting in a low-cost, nonvolatile memory solution with excellent data retention and higher reliability. The split-gate NOR SuperFlash architecture facilitates a simple and flexible design suitable for high performance, high reliability, small or medium sector size, in- or off-system programming, and a variety of densities, all in a single CMOS-compatible technology. About Silicon Storage Technology, Inc. Headquartered in Sunnyvale, California, SST designs, manufactures, and markets a diversified range of nonvolatile memory solutions, based on proprietary, patented SuperFlash technology, for high-volume applications in the digital consumer, networking, wireless communications, and Internet computing markets. SST's product families include various densities of high-functionality flash-memory components, flash mass-storage products, and flash microcontrollers. SST also offers its SuperFlash technology for embedded applications through its world-class manufacturing partners and technology licensees, including Grace Semiconductor Manufacturing Corporation (GSMC), IBM, Motorola, National Semiconductor, NEC Corporation, Oki Electric Industry Co. Ltd., Samsung Electronics Co. Ltd., SANYO Electric Co., Ltd., Seiko Epson Corp., Shanghai Hua Hong NEC Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), and Winbond Electronics Corp. TSMC offers embedded SuperFlash under its trademark Emb-FLASH. Further information on SST can be found on the company's Web site. Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, Calif. Telephone: 1(888)SST-CHIP              or (408)735-9110 FAX: (408)735-9036 E-mail: sfoster@sst.com Web: www.sst.com The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Emb-FLASH is a trademark of TSMC. All other trademarks or registered trademarks are the property of their respective holders.

More In a NOR We have seen NAND architected flash reach 2-Gbit densities, while NOR parts are in the 16- to 32-Mbit range. It would seem from that simple statistic that those who need density would shift over to NAND, but there is more to it than that. NAND parts are synchronous by their nature, and have block or sectored reads. The simple select, address, and read cycles of the standard NOR architecture are replaced by commands, responses, and block moves. This puts NAND and NOR parts in different arenas. While synchronous types of flash memories have been all the rage, asynchronous architectures are still needed and used in most applications. The true random-access abilities without pipeline penalties are a benefit, and the ease of use keeps these architectures alive and well. For real high-speed applications, contents mush be cached into higher speed SRAM or DRAM. But this one-time penalty doesn't affect performance after that, and the ability to execute directly from NOR flash is a big plus. The other benefit to NOR parts is that they are typically more error-free. NAND parts can be shipped with defective sectors that users must wear level, map, and lock out if they need error-free reliability. The synchronous architecture has had a benefit when it comes to writing speeds. Once the pipeline is in place, sectors can be clocked in at a higher speed. But, thanks to advances in NOR technology, this is not the case anymore. SST has just introduced its SST39VF320 32-Mbit (2M × 16) CMOS NOR flash that achieves a typical chip-erase performance 1,000 times faster than competing 32-Mbit flash alternatives according to SST. Based on the company's 0.18 µm self-aligned SuperFlash process technology, the new 32-Mbit part is an extension of its Multi-Purpose Flash (MPF) product family. While read access times are pretty standard at 70 and 90 ns, the erase and write times are pretty good. Erase takes only 40 ms instead of the one or more minutes typical with most Flash alternatives of this density. As for in-system programming, individual sectors can be erased 50 to 100 times faster than conventional flash (18 ms per 2Kword sector). Programming speeds are typically 7 µs per word. I like the small and uniform 4K per sector sizes. This helps these parts drop into sockets intended for other parts with larger block sizes because the 4K is a uniform denominator. Firmware may have to be modified if it was not initially coded to handle alternative sourced devices. I really like the data retention spec of 100 years. SSTıs SuperFlash technology uses a split-gate cell architecture. This takes advantage of a reliable thick-oxide process with fewer manufacturing steps. This helps reduce costs and helps provide the excellent data retention and higher reliability. Another feature I like is the Auto Low Power mode. This reduces the typical IDD active read current to the range of 2 mA/MHz of read cycle time. In order for this to work, the device exits the Auto Low Power mode with any address transition or control signal transition, which is used to initiate another Read cycle. As needed to make this useful, there is no access-time penalty. The overall result is low power consumption of 9 mA active current (typ.) and a standby current of 3 µA (typ.). The SST39VF320 is based on SSTıs 0.18 µm process, which is fabbed by three leading foundries—TSMC, Samsung, and Vanguard. The SST39VF320 uses a single voltage of 2.7–3.6 V for read and write operations. In addition to the more standard JEDEC standard pinout 48-lead TSOP (12 mm × 20 mm), the SST39VF320 is also offered in the industryıs smallest TFBGA package (6 mm × 8 mm).

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