The manufacturer says . . .

ChipCenter's Jon Gabay says . . .

SAN JOSE, Calif.--March 10, 2003--Cypress Semiconductor Corporation (NYSE: CY), a leading SRAM supplier, announced that its six-transistor 90 nm RAM9™ process technology has achieved functional silicon of the world's highest density SRAM. Operating at OC-48 speeds and above, the 72-Mbit synchronous SRAM supports next-generation networking applications. "The development of the 72-Mbit synchronous SRAM on a 90 nm footprint solidifies our leadership in both the networking SRAM market and technology innovation," said Antonio Alvarez, senior vice president for Cypress's Memory Products Division. "Offering the highest density SRAM in the market today, this product is the first of many to be migrated onto the RAM9 process by the end of the year." "Communication customers continue to seek higher density, cost-effective SRAMs for high-speed networking applications," said Betsy Van Hees, senior memory analyst for iSuppli Corporation. "With Cypress's recent development of the 72-Mbit synchronous SRAM on 90 nm process technology, they have proven their ability to be a leader in the SRAM market. Cypress now offers a leading-edge product that is ahead of their competition." RAM9 is being implemented in Cypress's Fab 4 in Bloomington, Minnesota. In addition to the 72-Mbit synchronous SRAM, two other product families are currently in design and will achieve functional silicon by late 2003 and early 2004. These product families include Cypress's next-generation networking Quad Data Rate™ (QDR™) SRAMs that operate at data rates beyond 300 MHz, and low-power More Battery Life™ (MoBL™) SRAMs, which use less power than standard SRAMs. Samples Samples of the 72-Mbit synchronous SRAMs will be available during the second half of 2003. About Cypress More information about Cypress is accessible online at www.cypress.com. Quad Data Rate™ SRAM and QDR™ SRAM comprise a new family of products developed by Cypress, IDT, Micron Technology, Inc., NEC, and Samsung. Hitachi has signed a letter of intent to join the QDR co-development team, and is currently finalizing a formal agreement with the other QDR team members. Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. "Connectivity from Last Mile to First Mile," "Cypress Connects," More Battery Life, MoBL, and RAM9 are trademarks of Cypress. All other trademarks are the property of their respective owners.

Almost Half-a-Billion-Transistor SRAM Remember when 1-million-transistor IC's were big news? This wasn't too long ago. Critics were saying "With that many transistors, reliability will be low, yield will be low, manufacturing would be difficult, and parts would be overpriced." Well, that wasn't the case. I recently reported on a 300-million-transistor network processor, and these numbers are almost common-place these days. But at what point will these concerns resurface? In a "keep it simple stupid" world, aggressive designs will eventually reach brick (or silicon) walls. I wonder how close this wall is with the new announcement from Cypress. Cypress is a leader in memory technology, with good capabilities and an impressive track record. They are just now announcing the success of the new 90 nm RAM9 process, which gives them an edge in producing the world's densest devices. Their first major thrust in this technology will be a 72-Mbit synchronous SRAM supporting next-generation networking applications for OC-48 speeds and above. These 2M × 36 and 4M × 18 NoBL (no bus latency) parts will be the first of many products to be migrated onto the RAM9 process by the end of the year. I like the performance—fast clock speed up to 250 MHz and fast access times down to 2.6 ns. I am a bit concerned with a few claims and approaches. First, they claim it to be world's highest density networking SRAM. While it is true that these parts are aimed at networking applications, a not-so-well-known company, MoSys, has been manufacturing a 96-Mbit SSRAM for over a year now. Although this 96-Mbit part was custom-developed for the gaming industry, it is still the densest part of its type I know of. Second, Cypress uses a 6-transistor cell. This translates into 432,000,000 transistors just for the memory array. Add row and column logic, decode logic, and I/O logic, and you are up to around ½ a billion transistors. This is very aggressive in my book, especially since 6 transistor cell-memory elements are susceptible to alpha radiation, yielding soft errors. On an array of this size, this is a real concern to me. When questioned, Cypress says they are aware of soft-error concerns, and feel confident there parts will perform well. To date though, soft-error tests have not been completed and results are not available. Many (like MoSys) have gone the route of the 1T/1C architecture, which is sort of like a pseudo-static design. This alternative architecture, which uses only 1 transistor (and 1 capacitor) for each memory bit, is very attractive since it reduces the transistor count dramatically and is less susceptible to soft errors. Cypress did announce a partnership to develop a 72-Mbit part that was supposed to be out by now, but this project is delayed for unspecified reasons according to Cypress. But, it is still on their roadmap. 1T/1C architectures do require internal refresh, but the die size is reduced and the reliability is said to increase. On the down side, standby power is higher with 1T/1C parts since internal refresh must take place even when parts are not being accessed. Reverse leakage can be an issue to with 1T/1C devices, and contributes to the power use. Low power is one of the benefits Cypress claims for the new 72-Mbit parts. They are also very confident that they will achieve high yields and excellent performance using the 6T architecture, which is their core competency. They already have 32-Mbit parts that are working well fabbed on the older lines. Another reason for the 6T approach was to keep latency low. Because the 6T structure can guarantee single-clock-cycle random accesses, Cypress feels this is an advantage over the longer latency 1T/1C approach. If anyone can pull it off, Cypress can. Their fab in Bloomington, Minnesota, is already cranking out test parts. While packaging still takes place abroad, it's nice to see state-of-the-art fabs here in this country. The next parts to come out of this aggressive technology will be the same 72-Mbit densities, but in DDR and QDR flavors. These are planned to be announced by late 2003 and early 2004. The new 72-Mbit parts are using 3.3 or 2.5 V Vdd. The 3.3 V parts can operate at 3.3 or 2.5 V I/O. The 2.5 V Vdd parts can operate at 2.5 or 1.8 V I/O. A separate Vddq power-supply pin is used for I/O. The new parts are available in 119-ball bump BGA and 100-pin TQFP packages. A 209-ball BGA package and a 165-ball FBGA package will also be offered.

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