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IRVINE, Calif.--April 14, 2003--Continuing its pioneering tradition in flash-memory development, Toshiba America Electronic Components, Inc. (TAEC), with its parent company Toshiba Corporation (Toshiba) announced a modified NAND flash memory designed to simplify the integration of higher density memory solutions into advanced cell phones. Called "Chip Enable Don't Care" NAND, the new memory allows inexpensive NAND flash to be more easily combined in cell phones with other memory such as NOR, SRAM, and Pseudo SRAM to provide a simpler, more affordable alternative to meet the increased memory requirements of today's feature-rich phones.
"High-density NAND flash is approximately 40 to 50 percent of the cost of NOR flash, offers faster programming and erase times, and requires less space because of its small cell size," said Brian Kumagai, business development manager, NAND Flash, for TAEC. "By simplifying the design challenge of integrating a memory subsystem that combines SRAM, PSRAM, NOR, and NAND, our new 'Chip Enable Don't Care' NAND helps make NAND flash an attractive alternative to cell-phone designers for the application and storage memory required in advanced mobile phones."
One of the challenges facing designers of advanced cell phones is the memory subsystem required to support auxiliary applications such as Internet browsing, text messaging, games, and even digital-camera capabilities. Not long ago, a typical talk-only mobile phone used 4 Megabits (Mb) to 8 Mb of low-power SRAM for phone-number data storage and 16 Mb of NOR flash for code storage. The additional applications found in today's feature-rich mobile phones have increased typical memory requirements to 8 Mb to 16 Mb of low-power SRAM for data backup, 32 Mb to 128 Mb of DRAM or Pseudo SRAM for movie or music working area, 128 Mb to 256 Mb high-speed NOR flash for bootable code storage, and 128 Mb to 256 Mb or more additional memory for application software and storage.
With its lower cost and small cell size, NAND flash is an attractive alternative for additional storage memory in these phones. However, the use of conventional NAND flash in many systems required extra design effort and/or the use of glue logic. Conventional NAND flash requires that the chip-enable signal line be asserted low during the entire read cycle, which will prevent the processor from communicating with other devices on the same bus. Glue logic or more complex memory bus designs were required to work around this characteristic, which is one of the reasons that NAND flash has not been widely adopted for storage memory in cell phones.
The new "Chip Enable Don't Care" NAND allows the chip-enable signal to be deasserted during the "read busy" period. This means that the microprocessor can communicate with other devices on the bus such as SRAM, PSRAM, or NOR flash while the NAND retrieves the information requested. The modifications in this new NAND flash device allow the read command to continue even if the chip-enable signal is deasserted, leading to the name "Chip Enable Don't Care." This feature also allows the processor to communicate with I/O devices during the "read busy" period.
Toshiba's "Chip Enable Don't Care" NAND is available in 128 Mb and 256 Mb densities, designated TC581282AXB and TC582562AXB. The 3.3 V flash-memory devices are available in BGA or stacked multi-chip packaging (MCP) combined with other memory products to support a variety of applications. Toshiba offers a wide selection of MCPs that combine NOR, SRAM, NAND, and Pseudo SRAM to provide flexible memory solutions for mobile-electronics devices. MCP packaging provides a smaller footprint and lighter weight solution specifically designed to meet the needs of cellular phones.
Product Specifications
| Part Number |
TC581282AXB |
TC582562AXB |
| Configuration |
528 bytes ×
32 pages ×
1024 blocks
(128 Mb) |
528 bytes ×
32 pages ×
2048 blocks
(256 Mb) |
| Power Supply |
VCC =
2.7 V to 3.6 V |
VCC =
2.7 V to 3.6 V |
| Page Size |
528 bytes |
528 bytes |
| Block Size |
(16K + 512) bytes |
(16K + 512) bytes |
Programming Time
(per page) |
200 ms typical |
200 ms typical |
Erase Time
(per block) |
2 ms typical |
2 ms typical |
| Access Time |
25 ms first access (maximum);
50 ns serial access (minimum) |
25 ms first access (maximum);
50 ns serial access (minimum) |
| Package |
7 × 10 BGA
Measures 7 × 10 × 1.2 mm
or MCP |
9 × 11 BGA
Measures 9 × 12 × 1.2 mm
or MCP |
Pricing and Availability
Toshiba's 128 Mb TC581282AXB and 256 Mb TC582562AXB "Chip Enable Don't Care" NAND flash devices are available now, priced at $7.00 and $12.00 each, respectively, in sample quantities. Toshiba's "Chip Enable Don't Care" NAND devices will be produced at the company's advanced manufacturing facility at Yokkaichi, Japan.
NAND Flash Background
Toshiba is a recognized pioneer in flash technology. Toshiba invented NAND flash technology in 1989. NAND flash is becoming one of the leading technologies for solid-state storage applications because of its high-speed programming capability, high-speed erasing, small block size, and low cost. The sequential nature (serial access) of NAND-based flash memory provides notable advantages for these block-oriented data-storage applications. Toshiba's NAND flash-memory products are optimized for general solid-state storage, image file storage, and audio for applications such as solid-state disk drives, digital cameras, audio appliances, set-top boxes, and industrial storage. These newly announced devices for use in mobile electronics products complement the company's current solid-state storage solutions.
Toshiba's existing line-up of NAND flash memories includes an array of devices available in Thin Small Outline Package (TSOP), ranging in densities from 64 Mb to 1 Gb. Toshiba also offers a wide range of small-form-factor storage solutions optimized for general solid, image file, and audio storage, including CompactFlash™, Smart Media™, SD Card, Multi Media Card (MMC), and ATA Card devices. For industrial use, Toshiba's NAND Flash Drive, announced in 2001, offers 2 GB storage capacity compatible with hard-disk drives.
About TAEC
Combining quality and flexibility with design-engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash-memory-based storage solutions, optical-communication devices, displays, and rechargeable batteries for the computing, wireless, networking, automotive, and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's Web site at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
CompactFlash is a trademark of SanDisk Corporation. SmartMedia is a trademark of Toshiba Corporation. All other trademarks and tradenames are the properties of their respective holders.
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Blockus Interruptus
NAND flash memory has really made a mark in technology. While standard NOR flash is great for nonvolatile code storage and execution, the very high density of NAND has opened the gateway for great applications like digital cameras, MP3 players, voice recorders, advanced PDAs and cell phones, solid-state disks, and more.
But the architecture has not lent itself to all applications because of some basic limitations.
First, it is not a true random-access device. Instead, sectors are streamed into and out of it synchronously. This means it is not very usable as a store-and-execute code block for a microprocessor or microcontroller.
Second, because of its synchronous-block architecture, it is not very bus-friendly, especially when real-time applications are running. Once a block read or write is to take place, the NAND flash keeps the bus captive until the entire cycle ends. With a 512 byte sector, this time can add up.
Some clever manufacturers have tried to address the first issue by creating a special mode on power-up that allows small blocks of memory to be read out byte by byte with a single clock. This can be code that loads a boot loader that sequences the rest of the large memory arrays. But the second issue still persisted until now.
Toshiba has created what they call the "Chip Enable Don't Care" NAND flash. This is a modified NAND flash memory designed to simplify integration of higher density memory solutions into advanced cell phones and other applications that need high-density storage, but also can't hog the bus.
The key is to allow inexpensive NAND flash (NAND flash is approximately 40 to 50 percent of the cost of NOR flash) to be more easily combined with other memory such as NOR, SRAM, and Pseudo SRAM on a unified bus.
The new "Chip Enable Don't Care" NAND allows the chip-enable signal to be deasserted during the "read busy" period. The result is that the microprocessor can communicate with other devices on the bus such as SRAM, PSRAM, or NOR flash while the NAND retrieves the requested information.
The modifications in this new architecture allow the read command to continue even if the chip-enable signal is deasserted. Thereby the name, "Chip Enable Don't Care." Processor I/O functions as well as DMA can take place during the "read busy" period. The result is a much more time-responsive design that is not locked into a long "wait state" while the NAND flash does its thing.
"Chip Enable Don't Care" NAND comes in 128 Mb and 256 Mb densities initially. The part numbers are designated TC581282AXB and TC582562AXB respectively. These are 3.3 V flash-memory devices placed in BGA packages.
The other plan for these parts is to put them in mixed memory stacks. The resulting stacked multi-chip packaging (MCP) parts will combine with other memory parts like NOR, SRAM, and Pseudo SRAM to provide flexible memory solutions for mobile-electronics devices since MCP packaging provides a smaller footprint and lighter weight solution than individual chips.
The problem is that everybody will want a slightly different flavor or size of the individual constituent memory parts. Therefore, for Toshiba to make the stacked parts work from a standard part point of view, they will have to combine the right densities and hit an application sweet spot. Cell phones are the first target, and time will tell if Toshiba gets it right.
It is true that if a design is slated for high-enough production runs, Toshiba can make a custom stack for you. Remember though that this will involve NRE and turnaround time. The nice thing about this approach is that it is possible to mix an ASIC or a microprocessor in the fray, making the smallest solution possible to date.
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