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Slow, Simple, Successful—TI's Sub-Gigabit SerDes Transceivers Offer Reach, Robustness, and Reasonable Pricing

Ideal for backplanes and serial interconnects where power, price, and performance are all important, these little beauties are just waiting to find homes in wireless base station interconnects and backplanes for mid-range networking equipment.

The manufacturer says . . .

Chipcenter's Lee Goldberg says . . .

New Second-Source Solutions Enable Greater Data Rate Range, Longer Transmission Distances Than Previous Devices Dallas, Texas--Extending its leadership in serving wireless infrastructure requirements, Texas Instruments Incorporated (TI) announced a line of serializer-deserializer (SerDes) solutions designed to transmit data over high-speed backplanes using 25 percent less power than competitive devices. Designed as drop-in replacements for existing market solutions, the new 10:1/1:10 SerDes devices offer improved operating characteristics that permit a wider data rate, longer transmission distances, and easier design than previously available products. Among the applications that will benefit from these improved features are wireless base stations, data communications backplanes, video and industrial systems. TI's SN65LVDS1023/1021 Serializer-Transmitters and SN65LVDS1224/1212 Deserializer-Receivers provide data throughput over low-voltage-differential signaling (LVDS) backplanes at rates from 100 to 660 Mbits/s. TI's SerDes products require less than 400 mW of power at 660 Mbits/s to convert 10-bit words into single-bit data streams, transmit the data over cable or copper backplane media, then receive and reconvert the data into 10-bit words again. Featuring a flow-through pinout for ease of design, TI's new SerDes solutions provide a second-source drop-in replacement for existing products in the market. Unlike other devices, however, the TI solutions support a wider frequency range, from 10 to 66 MHz, enabling designers to achieve a wider range of data rates in the same system. An increase in voltage swing by 30 percent over competitive products supports greater backplane transmission distances. Improved jitter characteristics help simplify board design and save system costs. More Channels, Less Space "TI's new low-power LVDS SerDes products enable base station and other backplane customers to pack more channels into less space more cost-effectively than ever," said Atul Patel, High-Speed Communications and Controls Product Marketing Manager at TI. "Customers can come to TI for complete backplane solutions and system-level support that satisfy their design needs now and provide a roadmap for future development." Other features of the LVDS SerDes devices include synch mode and lock indicators that facilitate design, verification, and troubleshooting. Characterization for the industrial temperature range of -40 to 85°C makes the devices more widely useful in extreme environmental conditions. The CMOS process used in manufacturing the devices lowers costs and offers the potential for integration with other CMOS functions as market requirements develop. The new low-power SerDes solutions complement TI's wide portfolio of SerDes products, supporting data rates up to 10 Gbits/s. Customers who design with the low-power devices have a range of SerDes solutions available from TI for future redesigns of their backplane products. Other high-performance TI solutions designed for use in wireless infrastructure include operational amplifiers, data converters, power management solutions, digital signal processors (DSPs), and application-specific integrated circuits (ASICs). Availability, Packaging, and Pricing TI's new SerDes solutions are available in a 28-pin shrink small outline package (SSOP). Planned pricing for all devices is $5.40 each in quantities of 1,000. Availability is scheduled as indicated in the table below.

I try to not write about the same company two weeks in a row, but in this case, I think TI has a second good idea that justifies bending my own guidelines. For the most part, I focus my coverage on the screaming-fast, multi-gigabit technologies for transceivers, switches, network processors, and backplanes, but there is often an even larger variety of applications for stuff that's a step or two back from the bleeding edge. In this case, TI has wisely spent some time polishing the technologies and chips to address the sub-gigabit backplane/interconnect market. Unglamorous as it may seem, the kinds of products that these medium-rate SerDes chips support will comprise a major chunk of the networking boxes sold this year. Capable of supporting data rates from 100 Mbits/s to 660 Mbits/s, the SN65LVDS1023/1024 and SN65LVDS1021/1212 chip sets employ a robust LVDS-based SerDes connection that is well-suited for applications like wireless base stations that run over a backplane, or even a short-run cable to connect signals within a chassis. For example, in a base station, it's an ideal way to connect a rack's controller card to its complement of radio cards. Industrial networks will also find great utility on the transceiver's emphasis on lower power, longer reach, lower noise, and higher densities. To accomplish this TI has integrated the SerDes, CDR, and line-coding functions on a single chip using their 0.025 & 0.2 µm analog fab technologies. Incidentally, they say they'll be migrating to 0.125 µm next year for selected products. The devices take a 10-bit parallel input from an optical link, a framer, or other source, and output an LVDS serial signal with an embedded clock. In intra-chassis connections for telecom applications, the embedded clock is a real plus because it simplifies cabling. TI says that the integration plus good analog design has allowed them to cut the chip's power requirements by 25% while providing a Vod (output swing) that is 30% larger than competitors. This translates directly to better range and noise immunity. They have also tightened the chip's jitter specs with a two-pronged approach. First, the designers widen jitter tolerance at the receiver by sampling the incoming signal to recover the clock using circuitry that places the samples more precisely in waveform. Transmit jitter is then reduced by using a highly stable PLL borrowed from a series of 2.4 GHz transceivers. Much like their faster counterparts, these chips employ pre-emphasis (non user-programmable) to extend reach. Theses clever little critters ramp up the amount of emphasis they put into the front of the waveform as the signal speed increases—up to 20%. Because of the relatively low speeds involved, TI says there is no need for equalization. Even without it, the pre-emphasis has increased reach in LVDS-grade cable up to 10 m, and up to 32" in regular PCB backplanes (more with very good connectors and careful PCB design). Lee's Vapor Index Rating: Click here for an explanation of the Vapor Index Rating.

SN65LVDS1023/1021 Serializer-Transmitters and
SN65LVDS1224/1212 Deserializer-Receiver Availability

Device	Data Rate Range (Mbits/s)	Input Clock Range (MHz)	Samples	Production
SN65LVDS102310:1 Serializer-Transmitter	300–660	30–66	Now	April
SN65LVDS12241:10 Deserializer- Receiver	300–660	30–66	March	June
SN65LVDS102110:1 Serializer-Transmitter	100–400	10240	Now	April
SN65LVDS12121:10 Deserializer-Receiver	100–400	10–40	March	June

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