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Simulating a Phase-Locked Loop Using a Sigma-Delta Modulator to Attain Nearly Arbitrary Frequency Resolution Without Spurs

by Andy Howard
Agilent EEsof EDA

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Introduction
Basic Phase-Locked Loop Operation
Fractional-N Synthesis to Achieve
   Finer Frequency Resolution
Fractional-N PLL Simulation
Accumulator Modeling
Fractional-N Cosimulation Results
Using a Sigma-Delta Modulator to
   Eliminate the Spurs
Using a Multistage Sigma-Delta
   Modulator Architecture
Summary

Introduction
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It is often desirable to create a phase-locked loop (PLL) with a frequency resolution in steps smaller than the reference oscillator frequency. This is often accomplished with a fractional-N PLL in which the divide ratio is varied between N and N + 1 at a defined rate. However, this technique generates undesired spurs. An alternative is to use a sigma-delta modulator, a circuit in which the divide ratio is "dithered" and the spurs are eliminated. This paper covers the basic phase-locked loop operation, fractional-N PLL simulation, and sigma-delta PLL simulation.

Basic Phase-Locked Loop Operation
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Figure 1 shows a block diagram of a basic phase-locked loop. This PLL consists of a reference source, a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a divider. If the divide ratio is a constant, the loop forces the VCO signal frequency to be exactly N times the reference signal frequency. The phase/frequency detector and charge pump deliver either positive or negative charge "pulses," depending on whether the reference signal phase leads or lags the divided VCO signal phase. These charge pulses are integrated by the loop filter to generate a tuning voltage. The tuning voltage changes the VCO frequency up or down until the phases of the reference signal and divided signal are synchronized.

Figure 1 - Basic Phase-Locked Loop

Phase-locked loops are used as frequency synthesizers in many applications where it is necessary to generate a precise signal frequency with low spurs and good phase noise. A VCO's signal frequency may be changed by varying either the reference signal frequency or the divide ratio. The reference signal is very often produced by a stable oscillator whose frequency cannot be varied, so the divide ratio is changed in integer steps to change the VCO frequency, where F_out = N * F_ref.

One limitation with this type of phase-locked loop is that the VCO frequency cannot be varied in steps any smaller than the reference frequency. With a little more circuit complexity, a 1/M divider could be placed between the reference signal and the phase/frequency detector, in which case the VCO output frequency would be determined by the ratio of the integer dividers, where F_out = (N/M) * F_ref.

Even when the loop is locked, the charge pump still outputs small charge pulses caused by mismatches in the PLL's positive and negative charge pumps and other factors such as non-ideal phase/frequency detection. These pulses cause sidebands, or spurs, to appear in the VCO output spectrum at offset frequencies equal to the reference frequency.

Dealing with these spurs requires some design tradeoffs. For a fine frequency resolution, we want a small reference frequency, but this will cause spurs to be generated at a smaller offset frequency from F_out. This means that a narrower loop filter bandwidth is required to filter them. PLLs with narrower loop bandwidths have longer transient settling times (the transition time from one frequency to another) and may not operate at the required speed. Reference [1] has a discussion of PLL settling time requirements. Also, the narrower the PLL's loop bandwidth, the less the VCO's phase noise outside the loop bandwidth is suppressed.

Fractional-N Synthesis to Achieve Finer Frequency Resolution
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Fractional-N is one popular technique that achieves a frequency resolution that is finer than the reference frequency. In this approach, the divide ratio is varied periodically between two integer values. Figure 2 shows a block diagram of this type of PLL.

Figure 2 - Fractional-N Synthesizer PLL

The average VCO frequency is determined from Equation (2) in Reference [2], which is repeated here.

_vco

_ref

_n+1

_ref

_n+1

which can be reduced to

_vco

_n+1

_ref

Therefore, the fractional part of the divide ratio is determined by the duty cycle, the fraction of the time that the divider is dividing by N + 1.

This type of PLL may be modeled using an accumulator that sums the desired fraction to itself each reference clock cycle (Reference [2]). While the accumulator's sum is less than its total count capacity, the overflow output is 0, and the divider divides by N. When the accumulator reaches its capacity, it overflows and the divide ratio is set to N + 1. If the desired fraction is 0.1, the accumulator will overflow once every 10th reference clock cycle. If the desired fraction is 0.5, the accumulator will overflow every other reference clock cycle.

In fractional-N PLLs, the signals at the input to the phase/frequency detector are not at the same frequency. The reference signal is at F_ref, and the divided VCO signal is at (1 + fraction/N) * F_ref. Referred to the VCO, this frequency difference means that the phase of the VCO advances at a rate of fraction radians per reference clock cycle faster than a signal at frequency of N * F_ref. The accumulator sums this fraction once per reference clock cycle, so it accumulates at the same rate that the VCO phase difference advances. An accumulator overflow occurs at the same time the VCO phase difference (relative to a signal at N * F_ref) reaches 2p radians. When the accumulator overflows, the divide ratio is increased to N + 1 for one cycle. This subtracts 2p/N radians from the divided VCO signal, so the phases of the two signals at the input to the phase/frequency detector are again equal. Thus, the phase difference between the two signals at the input to the phase/frequency detector should increase and be reset to zero at the same rate that the accumulator sum increases and overflows. A numerical example is given in Reference [2].

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