DAC 1998

By Murray Disman

The Design Automation Conference was its usual madhouse of people and parties. The number of silicon-oriented companies exhibiting has been increasing steadily over the past few years and almost every PLD company had an exhibit at this year's meeting. A special section of the exhibit floor was set aside as Silicon Village to encourage participation.

Some of the PLD companies had booths on the regular exhibit floor as well as in Silicon Village. Several companies only had booths on the exhibit floor and several were located only in the village. All of the participants agreed that the booths on the regular exhibit floor attracted much more traffic than those locations in Silicon Village. Current plans call for Silicon Village to be repeated next year.

Much of the emphasis at the conference was on the various aspects of "system-on-a-chip" implementation. However, most of the interesting product introductions were focused on the verification and debugging of designs. Both the large established companies and a host of new entrants described offerings to help alleviate the verification bottleneck that has arisen as a result of the trend towards higher levels of chip integration. The verification problem is being attacked at the highest levels of hardware/software co-design to the details of gate- and transistor-level timing.

Work is in progress to integrate Synopsys' Eagle hardware/software co-verification tools with Quickturn's verification tools to provide a platform for the early development and debugging of software in embedded systems. The Eagle tools are being integrated to the emulation systems via Quickturn'' Q/Bridge co-simulation interface.

Improvements are being made in emulation techniques by both established suppliers and several new companies. Quickturn's Mercury, its latest verification system, uses both RISC processors and FPGAs for behavioral code simulation and RTL/gate emulation, respectively. Simulation is done in a parallel array of PowerPC403GCX 66Mhz RISC processors. The emulation part of the system is based on arrays of Xilinx XC4036 and XC5215 FPGAs. Each million-gate single-board module contains two RISC processors and 74 FPGAs.

Two new emulation tools from Aptix and Axis have been introduced that are based on Altera's EPF10K250A. Aptix is using the new device in an emulation board for its system, while Axis has developed a new approach to verification that is an add-in board for the PCI slots in Sun workstations. Like Quickturn's Mercury, behavioral code is simulated and the RTL code is emulated, but in a different way. Sections of the RTL code are directly mapped to processing modules constructed from the logic elements in the EFP10K250A.

Altera's EPF10K250A is due to begin formal sampling in several weeks and, at that time, it will be the largest available FPGA. Xilinx, with its XC4125XV, currently holds the logic-density lead and is due to introduce a member of the XV family later this year that is twice as large as the XC4125XV. Both the new Altera and new Xilinx devices will be at the extreme limit of what can be fabricated within a single reticle. It should be noted that the Altera FLEX 10KA devices are being made using a 0.35-micron process, while the Xilinx XV series are fabricated on a 0.25-micron process.

Work is continuing on C-to-HDL conversion software with a new tool from CompiLogic and a new introduction from Frontier Design. The primary features added to CompiLogic's C2Verilog Pro give the user greater control over the parallel execution of loop iterations and resource sharing and better definition of register arrays. The new $25,000 tool is aimed at data path and DSP applications.

The company described an interesting application in which a DSP algorithm was implemented in an FPGA. In this case, the developer of a JPEG image compression tool was reticent to deliver the actual code for customer evaluation. Instead it processed its software through C2Verilog and then implemented it in a QuickLogic FPGA using Synplicity's logic synthesis tool. The company was then able to deliver protected hardware versions of its image processing software.

Frontier Design, A Belgium company, introduced two tools aimed at creating and converting C-based algorithms to RTL code. These are A/RT (Algorithm-to-Register Transfer) Library for the development of fixed-point C-descriptions of algorithms and A/RT Builder for the direct conversion of C-based algorithms to VHDL or Verilog. A Unix version of A/RT Builder is scheduled for September availability with a price of $20,000, which includes A/RT Library.


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