Introduction

The format of the PLD Section of the ChipCenter has been changed and expanded to include a number of new links to other related sites and this Tech Notes section. The purpose of the Tech Notes is to provide a platform for the expression of opinions and the sharing of technical information concerning PLDs, their applications and their related design tools. While I expect that most of weekly articles posted in this section will be written by the vendors of programmable logic devices and design software, I would like to encourage the users of these devices and tools to participate.

It is really the designers using PLDs that determine vendor offerings. While in many cases this may be hard to believe, the vendors truly want to know what the designers think and what they need. There are two ways for the industry participants to use this section of the Design Center to express their views and to exchange information. The simplest way is to suggest areas to be covered or to ask questions by sending an e-mail to mdisman@chipcenter.com. I will try to get these topics covered in future Tech Notes.

Many of the topics we plan to cover will be ongoing areas of interest and/or concern. Previous Tech Notes will be available on the site so that the reader can compare the different points of view presented over a period of time.

The following is an introduction to the first series of the Tech Notes that will be published.

CPLDs Versus FPGAs
This series of Tech Notes will explore the historic and evolving roles of CPLDs and FPGAs in digital circuit design. The relative advantages and disadvantages of using one of the two different types of PLDs obviously depend on the details of the circuit being implemented. However, the recent changes that have occurred in terms of increased CPLD density and higher FPGA speeds have blurred the boundaries separating CPLDs and FPGAs. In addition, embedded circuitry on FPGAs to perform traditional CPLD roles and the availability, later this year, of Altera's Raphael family with both types on devices on a single chip will be complicating the designer's choice.

I suppose it is necessary at this point to define the difference between a CPLD and FPGA. Both types of PLDs are composed of interconnected arrays of blocks that contain a logic generator followed by a register, which can usually be bypassed. The logic generator in all CPLDs is a product-term matrix, while that in an FPGA it is most often a look-up table. There are a number of FPGAs on the market that use combinations of gates and/or multiplexers for the logic function. These include devices from Actel, Atmel, DynaChip, GateField, and QuickLogic. Atmel's latest FPGA family, however, is look-up table based.

The most widely accepted definition of a CPLD is that it is a device composed of a number of product-term arrays/register combinations that are interconnected by a switch. All other high-density PLDs are considered to be FPGAs. The product-term array is usually an AND array that is followed by a number of OR gates and registers. The number of inputs to the OR gates and the number of OR gate/register combinations, called a macrocell, vary from manufacturer to manufacturer.

The historical thinking about the relative advantages and applicability of FPGAs and CPLDs is shown in Exhibit 1. It is not unusual to find CPLDs and FPGAs on the same circuit board, with the different devices used for the circuit functions appropriate to their architectures. However, as previously stated, many of the distinctions between the two types of PLDs are beginning to blur.

Exhibit 1- Relative Advantages and Applicability of CPLDs and FPGAs

CPLDs	FPGAs
Control Logic State Machines Address Decoders Bus Controllers Priority Encoders Wide Functions Combinatorial Logic High Speeds Predictable Timing Moderate Capacity	Data Path Logic Register Files FIFOs Serial-Parallel/Parallel-Serial Bus Interfaces Narrow Functions Registered Logic Lower Speeds Timing is Routing Dependent High Capacity

One of the advantages of CPLDs is the ease and speed with which they can be designed. CPLDs are essentially interconnected collections of simple PALs, such as the familiar 22V10. PALs have been in existance for some 20 years and there is wide body of engineers familiar with their design and use. Another advantage of CPLDs is that they are the cheapest way to implement several hundred gates of programmable logic. Small CPLDs can now be purchased for a little more than one dollar, much less than one-half the cost of the cheapest FPGA. However, in many instances the FPGA is the less expensive solution for higher-density applications.

Future Tech Notes will investigate, in more detail, the advantages and disadvantages of CPLDs and FPGAs in different circuit applications. Many of these will be written by suppliers of these devices and can be expected to be somewhat biased. I would appreciate inputs from the readers on this subject.

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