FIFO Applications Enabled by Embedded RAM in FPGAs

By: John Birkner, QuickLogic Corporation (birkner@quicklogic.com)

Passing data across the asynchronous boundary from one system clock to another, is one of the most challenging issues in digital design. Indeed, one consultant exclaimed: "I've made pots of money on 911 calls to solve asynchronous system bugs." When system reliability is crucial, design engineers must understand MTBF parameters associated with FIFO implementation. And herein lies the biggest problem --that is, acceptance, even awareness, that such a problem exists.

Are you having trouble passing data from one system to another? Answer: use a FIFO -- you can buy them off-the-shelf. Of course they work. They must work or why else would vendors make them. The appropriate analogy here is to beware of salesmen selling snake oil to cure all ills.

Even synchronous FIFOs can be challenging. Have you ever noticed an erroneous random pixel pattern on the left vertical column of a CRT display? Chances are, this is a FIFO protocol system bug caused by some FIFOs that deliver data one cycle later than the not_EMPTY flag assertion which signals data available. That protocol may be fortuitous to a semiconductor vendor's data sheet specs or convenient for an IP core vendor's HDL code, but it can cause grief with a designer's state-machine interface to a FIFO.

FPGA Embedded RAM to the rescue
Take control of your destiny by spinning your own FIFO design, using embedded dual-port RAMs in FPGAs. The dual-port feature is crucial in separating the write-side of the RAM from the read-side, both architecturally and in time. Dual-port, as the name implies, separates both address and data from write and read operations as shown in figure 1. Any word in the RAM can be written simultaneously with the read operation of any other word. Simultaneous write and read of the same word, of course, must be avoided.

Figure 1. Write-side address decode is independent of read-side address decode as shown for one bit of Dual-Port RAM architecture, enabling simultaneous write and read operations in a FIFO application. Configure the width and depth of your FIFO to exactly fit your application requirements. Does your communications application require 9, 18, 36 or whatever, bit words to match unique requirements such as parity or error correction? No problem. Embedded RAMs provide a variety of configurations such as 512x2, 256x4, 128x9, 64x18 as in QuickLogic's pASIC3 FPGAs with RAM-on-board, allowing over 100MHz clock rates. You can automatically generate custom FIFO width and depth using IP core generators such as QuickWorks 7.1 RAM Module Creation Wizard, shown in figure 2, which creates Verilog, VHDL or schematic, complete with test bench/fixture.

Figure 2. Automatically generate custom FIFO width and depth using IP core generator with QuickLogic's QuickWorks 7.1 RAM Module Creation Wizard.

Does your application require unique flags beyond FULL and EMPTY, such as HALF_FULL, ALMOST_FULL, FULL_MNUS-7? Or, is your FIFO depth uniquely a non-power-of-2, say for instance, 100? Then you may easily customize an IP core generated FIFO by editing the HDL code to your specific requirements. Will the data be available in the immediate cycle when not_EMPTY signals data available? When you can modify the HDL code, you are in control.

Synchronous FIFO basics

The synchronous FIFO design utilizes Dual Port RAM for independent PUSH and POP operation with a common clock. Write data is pushed in the clock period that PUSH is asserted. Read data is popped in the clock period that POP is asserted. The FIFO can be cascaded by connecting not_EMPTY to PUSH and not_FULL to POP of adjacent FIFOs. Custom flags such as FULL_MINUS_7 can be added, simply by adding a comparitor and a write-side counter initialized to 7. The write and read state machines are described as follows:

Figure 3. Synchronous FIFO utilizes Dual Port RAM for independent PUSH and POP operation with a common clock.

Synchronous Write-Side State Machine
When the FIFO is not FULL and PUSH indicates that write data is present, data will be pushed into the write-side of the dual-port RAM at the write address pointer while incrementing the pointer. When the write pointer catches up with the read pointer, the FULL flag is set and remains set until POP is asserted.

Synchronous Read-Side State Machine
When the FIFO is not EMPTY and POP indicates that read data is requested, data will be popped from the read-side of the dual-port RAM at the read address pointer while incrementing the pointer. When the read pointer catches up with the write pointer, the EMPTY flag is set and remains set until PUSH is asserted.

Asynchronous FIFO Challenge

The synchronous FIFO above can be modified for asynchronous operation by, first, separating the single clock to write-side and read-side clocks, WCLK, RCLK as shown in figure 4. Next, the hold conditions for FULL and EMPTY must be equated to the compare of write and read pointers for equality. When these pointers are equal, FULL and EMPTY must stay set if either were set. Using not_POP to hold FULL, or not_PUSH to hold EMPTY, as in the the synchronous design, will not work across the asynchronous boundary shown in figure 4.

Figure 4. Asynchronous FIFO design maximizes MTBF by isolating the write and read state machines as two separate synchronous systems that communicate over the "asynchronous boundary" with the minimum number of combinatorial signals.

As the write-side and read-side state machine dependencies are purely combinatorial, the MTBF of the asynchronous FIFO is identically equal to the metastable characteristic of a single master-slave flip-flop. Occasional FULL and EMPTY conditions will assert and fall back according to the flip-flop metastable characteristics. The false assertions that occur due to binary rollover decode spikes can be reduced by using Grey-code counters. Even though the Grey-code sequence allows only single bit transitions, there will still be occasional metastable events, but at the minimum rate.

The strategy employed in this FIFO design maximizes MTBF by isolating the write and read state machines as two separate synchronous systems that communicate over the "asynchronous boundary" with the minimum number of combinatorial signals. The write and read state machines are described as follows:

Asynchronous Write-Side State Machine
When the FIFO is not FULL and PUSH indicates that write data is present, data will be pushed into the write-side of the dual-port RAM at the write address pointer while incrementing the pointer. When the write pointer catches up with the read pointer, the FULL flag is set and remains set as long as the read and write address are equal.

Asynchronous Read-Side State Machine
When the FIFO is not EMPTY and POP indicates that read data is requested, data will be popped from the read-side of the dual-port RAM at the read address pointer while incrementing the pointer. When the read pointer catches up with the write pointer, the EMPTY flag is set and remains set as long as the read and write address are equal.

Designer's Responsibility
If you are planning to use an asynchronous FIFO in a life-support system such as a pacemaker, or antilock braking system, or flight instrument landing system, your customers are counting on you to understand your system MTBF. If you are an astronaut blasting off to save the planet from a comet on collision course, realizing that your space shuttle contains over 200,000 parts supplied by the lowest bidder, your FIFOs had better work. Over the years, FIFO design has been a controversial subject. You have read my position. What is yours? Please share your comments, critique, criticism, and alternate design approaches. (birkner@quicklogic.com)

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