The great majority of the design is now done within the system design tool. SystemView by ELANIX provides a complete design flow starting from developing the 'ideal' design for a DSP or communication system, all the way through to the bit-width optimization required to minimize final gate count. In addition, SystemView by ELANIX includes tokens (functional blocks) that replicate the behavior of Xilinx's DSP LogiCORE products. By using these tokens, designers can build a complete 'implementation-ready' DSP application within SystemView by ELANIX itself. SystemView by ELANIX is integrated with the Xilinx CORE Generator, enabling a designer to automatically generate application-specific cores by simply clicking a button.

The new design flow eliminates many of the steps associated with developing applications using DSP processors, greatly improving time-to-market (Figure 1). Since the DSP LogiCORE products are already optimized for efficiency when laid out in Xilinx architectures, the designer may use Xilinx FPGAs without requiring a detailed knowledge of FPGA architectures.

Figure 1: The new design flow eliminates many of the complexities associated with developing and integrating DSP software

Subsequent sections of this white paper examine the specific benefits of SystemView by ELANIX and how it integrates with the Xilinx CORE Generator and DSP LogiCORE products in greater detail. For further information concerning the potential cost, performance, and power dissipation advantages of FPGAs for DSP applications, please refer to the 'Xilinx DSP - High Performance Signal Processing' paper from Xilinx.

SystemView by ELANIX
Digital communication and DSP applications offer an almost innumerable number of design trade-offs. For example, when determining the overall communications system, a designer must consider several different encoding and modulation techniques. Even when such high-level design decisions have been determined, individual filter design is itself complex. Designers must chose between different filters types, such as FIR and IIR, and determine tap counts and coefficient values.

Without a tool that enables rapid exploration of different design approaches, it is likely that a less than optimal algorithm may be selected. For example, a filter might use 16-bit data path when only 12 bits would have been sufficient. For applications using a flexible implementation methodology such as an FPGA, this would result in an unnecessary increase in final product cost.

SystemView by ELANIX is a system-level design tool that enables designers of DSP, digital communication, and RF/Analog applications to rapidly model, optimize, test, and debug their design at the system-level. Compared to first-generation DSP system-level design tools, SystemView by ELANIX offers an exponential increase in productivity. This advantage stems from the combination of SystemView by ELANIX's breakthrough user interface with powerful modeling, simulation, and analysis tools, which are discussed in further detail below:

Object-oriented design editing: SystemView by ELANIX provides a highly intuitive interface for building block diagrams models. Uniquely, new functional blocks automatically inherit characteristics such as sample rates, arithmetic modes, and bit-widths from the block immediately upstream. This eliminates the need to tediously enter these characteristics for each block and enables working models to be built much more quickly. As importantly, it also greatly shortens the time required to modify the characteristics of a complex system. For example, changing the bit-width of a DSP application modeled using 30 functional blocks takes a few seconds. SystemView by ELANIX's object-oriented design editing benefits fully support the design of multirate systems. Combined with its easy to use decimators and rate changers, SystemView by ELANIX enables even highly complex models to be quickly built and changed. These capabilities enable designers to perform exploratory 'what-if' analysis 10-100 times more quickly than with previous generation products.

Design flow that bridges gap between system engineer and digital designer engineer: Traditionally system designers have focused on determining an 'ideal' design that is based on single or double-precision floating point arithmetic. However, for cost reasons actual implementation is typically done in fixed-point integer arithmetic. As a result, the digital designer is faced with converting the ideal design into one that will be actually implemented in silicon. In cases where the final implementation will use FPGA or ASIC technology, the digital designer is not only concerned with ensuring that the fixed-point design adequately implements the ideal design but also with reducing filter coefficient and data path bit widths to minimize the overall gate count.

In the past, the digital design engineer has had few tools that adequately support fixed-point optimization. Often engineers have been reduced to writing 'bit-true' C models from scratch, a time-consuming and error-prone process. Another alternative is to write some initial HDL code and then prototype different ideas using a FPGA and A/D converters on a board. This is also a time-consuming process. Furthermore, tools such as C debuggers and HDL simulators do not provide adequate signal analysis tools, sometimes forcing engineers to write programs to plot numbers in a meaningful way. An added difficulty is that many digital design engineers lack expertise in DSP and communications theory.

SystemView by ELANIX completely eliminates these difficulties, enabling a process that often takes several weeks to be finished in a few hours. SystemView by ELANIX's intuitive analysis and modeling enable digital design engineers to instantly grasp fundamental DSP concepts. Because SystemView by ELANIX fully simulates bit-true DSP behavior, a digital designer can quickly experiment with different bit-widths on a fixed-point filter and compare them with the filter in an ideal design to verify the most efficient implementation.

Comprehensive system modeling: SystemView by ELANIX's extensive model libraries ý CDMA/IS-95, communications, DSP, RF/Analog, & TTL logic ý enable a designer to comprehensively model a communications applications without having to spend time developing models of specific functions. In addition, mixed-mode behavior, such as an FPGA-based DSP function interfacing to an A/D, can be modeled up-front, reducing the likelihood of encountering unexpected problems later in the design cycle.

High-performance simulation: SystemView by ELANIX provides high-speed simulation performance that is superior to other system simulators and orders of magnitude greater than HDL simulators. Simulation speed can be at least doubled by adding the Automatic Program Generator option. High-performance simulation reduces the time needed to evaluate different design trade-offs and enables comprehensive testing, such as BER runs, to be performed.

Powerful analysis and test tools: The complexity of communications and DSP applications make it inevitable that even the most experienced designers will make errors during the initial system design. Although logic simulators are excellent tools for general hardware debugging, they do not provide an efficient mechanism for observing complex DSP and communications behavior. In many cases, algorithmic errors may go undetected until a hardware prototype exists that can be exercised with test equipment such as signal generators and spectrum analyzers. Rectifying design flaws detected at this stage of the cycle is very expensive since a great deal of coding and debugging has already been completed and extensive retesting must be done.

By enabling a designer to quickly yet completely model an entire system up-front, SystemView by ELANIX enables much more comprehensive testing to be carried out at the system level, when the cost of rectifying a defect is much lower. SystemView by ELANIX's powerful collection of analysis, debugging, and test tools greatly simplify detection and resolution of signal processing and communications design problems.

In addition to the standard amplitude/time and power spectrum displays, SystemView by ELANIX's analysis tools include the powerful Sink Calculator. The Sink Calculator provides point-and-click access to over 70 mathematical functions, including auto- and cross-correlation, windowed spectral analysis, algebraic operations, and histograms, that can be used to process blocks of data generated by simulation runs. These functions enable designers to quickly produce sophisticated data plots such as QAM constellations or phase locked loop phase planes that allow at-a-glance analysis of complex facets of system behavior.

Once a problem has been detected, designers can use SystemView by ELANIX's dynamic system probe and stop sinks to help debug the model. The dynamic system probe enables a designer to interactively trace a signal through each block, looking for anomalies. The stop sinks act as 'break points' enabling the designer to stop the simulation or notify the designer if a certain condition is detected.

To automate the process of testing a system under many different conditions, SystemView by ELANIX provides global parameter variation. This enables the designer to set up a loop where each simulation run uses different parameters from a file, eliminating the need to manually enter different parameters. Global parameter variation enables tests such as BER runs to be accomplished in a single session without user intervention.

Integration with the Xilinx DSP design flow
Although a system-level design tool such as SystemView by ELANIX plays an important role in reducing design time, its value can be further increased through integration with design tools that address specific implementation paths. As a result, Elanix has partnered with Xilinx to provide a complete DSP application design flow for designers using FPGAs. This integration leverages Xilinx's Core Generator and LogiCORE products, which provide important advantages for DSP developers in their own right.

Figure 2: SystemView is integrated with Xilinx's DSP tools, providing a smooth flow from system-level design to silicon implementation

Xilinx's LogiCORE products include reusable IP cores for many DSP functions, such as FIR Filters and multipliers. To enable cores to be customized for a specific application, each core is highly parameterized. Therefore a designer can tune a core's functionality to precisely match that required by the application through setting the correct parameters. To simplify setting the parameters for a core, Xilinx provides the CORE Generator. The CORE Generator accepts simple text files that specify the appropriate parameters for each core, freeing the designer from having to modify HDL code to customize the core.

To enable designers to quickly identify the optimal parameters for each core, Elanix and Xilinx have worked to integrate SystemView by ELANIX with the CORE Generator. Each Xilinx DSP LogiCORE has a corresponding token in SystemView by ELANIX's DSP library. The addition of a Xilinx-specific option enforces correct parameter limitations on these tokens so that the designer cannot enter parameter values that are not supported by the LogiCORE itself. This option also enables the designer to automatically invoke and pass core parameters to the Xilinx CORE Generator. The CORE Generator then produces netlists of the fully parameterized cores, HDL simulation models, schematic symbols, and HDL instantiation code.

In future releases, SystemView by ELANIX will produce structural VHDL code, detailing the interconnectivity between the cores required to implement the whole DSP subsystem. This structural VHDL includes the instantiation code produced by the CORE Generator for each core. SystemView will automatically invoke the Xilinx Foundation VHDL editor so the designer can integrate the DSP subsystem with the remainder of the design.

Conclusions
This combination of SystemView by ELANIX and Xilinx's CORE Generator provides a faster and simpler methodology for designing high performance DSP applications. SystemView by ELANIX provides an easy-to-use visual design environment for DSP and communications applications, enabling the most efficient design to be quickly determined. SystemView by ELANIX is tightly integrated with the Xilinx CORE Generator and DSP LogiCORE products, providing a direct path to a high performance silicon implementation for DSP applications.