The Role of Intellectual Property in the System-on-a-Chip Revolution

Herman Beke, Frontier Design (herman_beke@frontierd.com)

Hambrecht & Quist estimates that in the year 2000 the total SIP (Silicon IP) market will be $20 to $25 billion. However, the company also believes that only $6 billion will be attributable to the merchant sale of "off-the-shelf" IP blocks. While most people talk about the merchant Silicon IP market, it is a fact that most intellectual property resides inside system houses as proprietary algorithms. During the next five years the vast majority of intellectual property will remain captive. Companies who have spent years developing and refining their algorithms will not go outside to acquire IP, because they will loose the competitive advantage they have worked so hard to acquire. Their IP focus is much more likely to concentrate on changing their in-house processes to produce proprietary IP cores of these proprietary algorithms themselves.

Most systems companies have historically become successful because of their systems know-how, not their silicon know how. Companies in fields such as wireless telecom, consumer electronics and multimedia have accumulated a wealth of algorithms, which allow them to create state of the art end-user applications. These algorithms represent the key in-house Intellectual Property that has evolved over years. There isn't any off-the-shelf IP that will have the sophistication or fine-tuning of these internally developed algorithms.

Furthermore, there is no such thing as "Plug-and-Play" IP yet. A great deal of work is involved in getting any externally developed core to work properly in a system. There are bussing and timing issues that can be very difficult to solve. Often the IP block must be customized to fit the customer's application. Most importantly, however, the IP core does not take advantage of the algorithmic IP that has been developed by these companies.

Thus, the challenge for the development of re-usable IP will not be in the area of developing off-the-shelf IP cores for sale to the merchant market. It will be in the area of taking the existing in-house algorithmic IP and turning it into performance-optimized and re-usable silicon IP blocks.

A new type of "Algorithm-to-Silicon" design methodology will need to be employed to achieve this goal. The methodology will need to be supported by a set of high level specification, analysis and synthesis tools that help the system designers to develop and refine their algorithms. In this scenario, the system designer specifies a bit true algorithm for behavioral simulation and verification, using test vectors coming from the real application. The algorithm is then converted to a synthesizeable VHDL or Verilog IP core. Although there are tools on the market that can assist designers is developing an RT-level description of the system that is optimized for power, area and/or performance, there is a significant learning curve involved in achieving expertise with them. Time to market pressures often prohibit designers from going through this learning curve.

In addition, most system houses prefer to do what they do best where the value of their effort is maximized -- system and/or algorithm design. Thus, a new type of EDA service is likely to evolve in which firms with the expertise to generate an optimized RT-level VHDL or Verilog core assist systems companies in turning their proprietary algorithms into re-usable silicon IP cores and then help integrate these cores into systems-on-a-chip.

For example, Phonak a leading innovator in the hearing instrument industry has substantial algorithmic IP developed for adaptive noise canceling and beam-forming techniques that enhance sound quality and improve communication in background noise. The company used an external SOC integrator to convert these algorithms to digital signal processing silicon IP cores and to integrate these cores into an SOC that could fit in a person's ear and would draw minimal power. The silicon know-how to optimize the SOC architecture to minimize die size and power consumption were not available within Phonak. By using the expertise of a silicon integration partner, Phonak was able to expend their own expertise where it had the most value, in the development of new hearing aid algorithms and filters. By using an SOC integrator the company was able to implement the new algorithms in silicon much more quickly, efficiently and cost effectively than if they had attempted this feat internally.

The most likely candidates to take on the role of Algorithm-to-Silicon IP core development and SOC integration are the EDA tool vendors. The EDA tool vendors have the technology to create new tools need to achieve this goal and the expertise to use them. But these tools should not be developed in a vacuum. They should be developed in conjunction with the systems companies that are the ultimate beneficiaries of the IP revolution. Thus strategic partnerships will need to be developed in which EDA tool vendors work closely with systems companies to enhance SOC design methodologies.

There are still companies who want to keep their entire design process in-house. Sony Corporation is one such company. In the design of a new sampling rate converter for its high-end Mini-disc Recorders, Sony used Frontier Design's DSP Station with the Mistral2 synthesis tool to create two cooperating custom DSP processor cores. Sony has already developed a unique asynchronous sampling rate conversion algorithm. The "Algorithm to Silicon" design flow integrated as part of Sony's design process. According to Nobiyuki Yasuda, Senior Engineer at Sony's Home audio & Video Products Division, "The Algorithm to Silicon design methodology embodied in DSP Station was instrumental in finding the most optimal decimation and interpolation filters. It allows us to simulate the fixed-point behavior of our algorithms before going to the RT-level. Mistral2 allowed us to find the most optimal architecture in terms of arithmetic resources, time schedule and memory usage."

Thus, the trend in intellectual property is more likely to be Silicon IP integration services than the development of intellectual property blocks for the merchant market. In order to survive, EDA tool vendors will have to develop a portfolio of IP blocks through internal development, in concert with customers, and through OEM agreements with merchant IP vendors. However, rather than selling these blocks like EDA tools, EDA vendors will have to focus primarily on consulting and integration services in order to help customers realize the benefits of creating and using their own as well as existing IP cores, and of integrating these blocks into complete silicon systems on a chip.


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