Using CPLDs to Simplify/Reduce Microcontroller Designs

By Brent C. Douglas, Lattice Semiconductor (bdouglas@latticesemi.com)

According to Dataquest, the fastest growing areas in the semiconductor industry are programmable logic and the microprocessor/controller markets. This may be a reflection of changing design methodologies. By combining microcontrollers, programmable logic devices (PLD), and advanced hardware description languages like VHDL, designers are able to shorten design and debug cycles while continuing to increase performance.

The PLD can benefit the microcontroller design by relieving the microcontroller of the "medial" tasks so that it can spend more time on true "processor" domain functions. In some cases, the PLD and more complex PLD (CPLD) can even replace the tasks of the microcontroller. Today's CPLD's are used to combine all the microcontroller interface functions as well as replace the microcontroller functions in the case where high speed operation of a function required. In other words, when special functions are implemented in hardware, they can run faster, at the speed of the hardware and not the speed of the code execution.

Although, it may initially seem easier and less time consuming to implement functions in the microcontroller, code implementations can quickly consume a designers time. Instead of designing a UART, for example, in logical functions with VHDL, one must think of them in terms microcontroller code. At this level, one is more likely to make mistakes, resulting in increased design/debug time. These delays could quickly stack up, resulting in delayed product schedules.

In addition, with CPLD operating speeds now in the 200 MHz region, timing critical operations can be performed while the microcontroller is doing other calculations. When ready, the microcontroller can access the data captured by the CPLD.

Unlike a microcontroller that is sequentially/interrupt driven, a CPLD can be configured to perform multiple special tasks. In other words, it is capable of performing many tasks at once. When doing many operations at once, tasks can be prioritized by the CPLD so that the most important operation is flagged for the microcontroller.

If a designer requires a microcontroller with a UART, a Serial Peripheral Interface (SPI), or an I²C interface, he or she has just reduced the selection of microcontroller available to use in a design. With a PLD, these functions could be easily implemented adding flexibility to the microcontroller choice. Furthermore, with in-system programming (ISP) capability, the CPLD can easily be updated to support new protocols, eliminating the need to redesign circuit boards.

With the use of simple handshaking signals, a CPLD can be used for bus arbitration. Allowing the CPLD to handle the bus arbitration would allow the microcontroller to stick to functions that require a microcontroller. In a sense, the microcontroller would "off-load" the arbitration to the CPLD.

In almost every microcontroller design, there is a need for logic to handle address decoding/mapping. This is an ideal application due to the flexibility offered by CPLDs. Using VHDL (or other HDL), a designer can painlessly allocate and merge memory banks, devices. This allows the microcontroller to access sections of contiguous memory, transparently reducing unnecessary software jumps. Also, CPLDs are capable of implementing "smart" logic; in which, they can be used to watch for pages of memory often accessed and cache then locally eliminating the need to access the memory through the bus.

Similarly, external devices such as I/O or data acquisition can be mapped in this manner. Because the data is passing through a logic device, special timers or events can be triggered or flagged when "special" data is present in the data. Again, this reduces the need for code in the microcontroller to constantly watch the data coming into the microcontroller.

Shifting operations can also be preformed in CPLDs at very fist speeds, if needed. These operations could also include parallel-to-serial or parallel-to-serial conversion.

In conclusion, adding a CPLD to a microcontroller design can save time and money in almost every stage of the design. In cases where high speed is a requirement, implementing a special function in a CPLD instead of a microcontroller allows hardware design flexibility. In the design stage, implementing functions in hardware will simplify code and allow for faster operation. In the manufacturing stage, boards can be easily debugged with the use of an ISP enabled CPLD. Using VHDL, designs can easily be modified to track down timing situations or modify the system should the hardware change.

Lattice Semiconductor Corp. offers many densities with the fastest speed available in the CPLD industry. In addition, devices are available that operate with a 5V core and 5V/3.3V I/O compatibility. If operating in a 3.3-volt system, Lattice can offer the same selection and high performance at 3.3V. As with all Lattice CPLD devices, the ispLSI devices are in-system programmable (ISP) allowing fast design debug, stream lined manufacturing, and field upgrade capability.


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