Overview:

Main Features

• ATM Forum UTOPIA Level-1 compliance
• Two cell transmit buffers and two cell receive buffers
• Transmits: Header Error Control (HEC) generation, IDLE cell generation, and cell payload scrambling
• Receives: Cell delineation, HEC verification, cell payload descrambling, and IDLE cell removal

Implementation:

These particular Cisco Systems products (PCIRunner, SpeedRunner, and FireRunner) provide a bridge between an ADSL bit pump and the ATM UTOPIA-1 bus interface. The bridge performs ATM Transmission Convergence (TC) sub-layer functions. The TC sub-layer performs five major functions, as shown in Figure 1. The following Receive and Transmit Modules to be presented below are the two main components of the Cisco Systems design, providing TC sub-layer functionality.

Figure 1. Physical layer of ATM Model, with appropriate functions.

Receive Module

The receive module is responsible for searching the incoming serial bitstream from the ADSL bit pump for the beginning of ATM cells. As valid cells are received, the data bytes are passed to one of the two receive FIFOs. When a full cell has been received, the cell is passed on to the UTOPIA-1 bus. The chief components of the receive datapath include the Cell Delineation Block (CDB), descrambler, a serial/parallel converter and two FIFOs.

Cell Delineation Block
An ATM cell consists of a four-byte header, followed by a one-byte Header Error Control (HEC) code. The remaining 48 bytes of the ATM cell contain data (see Figure 3 below). Cell delineation is the process of identifying a cell's boundaries from within the serial ADSL bitstream. The cell delineation process is described below. See Figure 4 for the state diagram of the cell delineation state machine.

Figure 3. ATM Cell Byte Allocation.

Figure 4: Cell Delineation State Diagram.

Header Error Control Verification
The serial input from the ADSL bit pump is loaded into a 40-bit shift register. With each clock pulse, the HEC is calculated across the last 32 bits of the shift register (assumed to be the first 4 bytes of cell header). This calculated HEC value is compared against the first 8 bits of the shift register (assumed to be the fifth byte of the ATM cell header, and HEC value for the current cell). In this mode, the receive state machine is in the HUNT state. If a match is found, the cell delineation circuit enters the PRESYNC state. See Figure 5 below for an example of the shift register used for calculating the HEC byte.

Figure 5. HEC state machine shift register.

While in PRESYNC mode, the circuit checks for the correct HEC at full cell (424 bit) intervals, as opposed to the single-bit intervals in the HUNT state. If an incorrect HEC value is found in the following cell, the state machine goes back to the HUNT state. If six consecutive cells are found to contain the same HEC value, the delineation process goes into SYNC mode.

Once in SYNC mode, the receive state machine continues to compare the HEC value of successive cells. The machine will stay in SYNC mode, assuming the HEC of each cell matches the correct HEC. Conversely, if seven consecutive cells are found to have a different HEC, the machine will go back into HUNT mode.

When the delineation machine is in PRESYNC mode, the payload data from the ATM cell is sent through a descrambling circuit. Once 43 bits of payload data are loaded into the descrambler circuit, the remaining payload bits will be properly descrambled.

During the SYNC state, the non-IDLE ATM cells with the correct HEC value are written to the internal receive FIFO. The incoming serial bitstream goes through a serial to parallel shift register, and the 8-bit data is written to one of the two FIFOs. When a full cell has been written to a FIFO, a signal is sent to the receive module, indicating that one of the ATM cells is ready to be sent to the ATM SAR, via the UTOPIA-1 bus.

Once the receive module has been notified that one of the FIFOs contains a full ATM cell, it begins to transmit that data, in 8-bit bytes, to the UTOPIA-1 bus. When the ATM SAR has read the 53rd byte of data, the receive module sends a signal to the cell delineation circuitry, indicating that it is ready to receive new cell data.

FIFO Specifications
Calculating how much on-board RAM the transmit and receive FIFOs require is a very simple equation. FIFOs for receive and transmit :

4 Bytes Header + 1 Byte HEC + 48 Bytes Data = 53 Bytes

• A single FIFO requires 53 Bytes = 424 bits of RAM.
• Two Receive Module FIFOs of 424 bits/FIFO = 848 bits of RAM total.
• QuickLogic dual-port RAM blocks are 1152 bit RAM blocks (shown in Figure 6), configurable in four modes. Each mode represents a unique configuration for the RAM block: 32 x 18, 64 x 9, 128 x 4, and 256 x 2. Multiple RAM blocks are available in the QuickRAMę family of devices. Depending upon the QuickRAM device being used, there are between 10 and 28 individual RAM blocks per device. This flexibility enables the designer the create one FIFO per QuickLogic RAM block, as shown in Figure 7.

Figure 6: 1152-bit RAM module.

Figure 7. Synchronous FIFO configured from 1152-bit RAM module.

Transmit Module

Figure 8. Block Diagram of Transmit Path.

The transmit module is responsible for receiving an 8-bit wide byte of data from the ATM SAR, via the UTOPIA-1 interface, and writing that data to one of two FIFOs. When a FIFO has been filled with the data from one cell, the ATM SAR is informed that another cell can be immediately sent to the other FIFO. In addition, the ADSL transmit state machine is updated with the current status of the FIFO that contains the full ATM cell, and the data can be output serially to the ADSL bit pump. The transmit datapath has several components, including an HEC generator, parallel/serial converter, scrambler, and two FIFOs.

Header Error Control Generation
The first four bytes of the ATM cell are used for the ATM header, and are clocked into the HEC generator circuit. The HEC generator uses the x8 + x4 + x + 1 polynomial as described in the ITU-T I.432 specification to calculate the HEC byte. This HEC byte is stored as the fifth byte of the ATM cell in the corresponding FIFO.

Transmitting Data to ADSL Output
When one of the FIFOs becomes filled with one complete ATM cell, the ADSL transmit state machine is alerted, so that the ATM SAR can begin sending another cell. The cell data is read from the FIFO eight bits at a time, and then passed through a parallel-to-serial conversion. After the conversion process, the data is written serially to the ADSL output, most significant bit (MSB) first.

The first five bytes from the FIFO are sent out in this fashion. The final 48 bytes of data represent the payload data of the ATM cell. These bytes go through the same parallel-to-serial conversion, but are subsequently sent to the scrambling circuitry before being sent to the serial ADSL output.

Scrambler
The scrambling circuitry is only used on the 48 bytes of payload data, and serves to enhance the performance and security of the cell delineation circuit that receives the data. The scrambling circuit utilizes the polynomial x⁴³ + 1 (found in the ITU-T I.432 specification). A 43-bit shift register is used to calculate the scrambled data to be sent out of the serial ADSL output.

When an ATM cell has been successfully transmitted, the ATM transmit state machine notifies the ADSL transmit state machine that one of the FIFOs has been emptied of its contents, and is ready for new data. At this point, both FIFOs are checked for the current status. If both are found to be empty, an IDLE cell is scheduled to be sent to the ADSL output. IDLE cells have an identifiable format, so that the receiving circuitry understands that they are not valid ATM payload data.

FIFO Specifications
The specifications for the Transmit Module FIFOs are identical the FIFOs described previously, in the Receive Module portion of this paper.

Choosing the FPGA:

QuickLogic devices also contain abundant routing resources, enabling designers to maintain a device pinout while going through several design iterations. The application's PCB can be manufactured with a specific pinout before the design has been completed!

A RAM Module Creation Wizard has been added to the latest version of the QuickLogic development tools, QuickWorksę (see Figure 9 below). The Wizard automatically configures the device's on-chip RAM banks to meet the designer's specifications for width, depth, and other characteristics. Every device in the QuickLogic QuickRAM family contains several RAM banks that can be configured into a FIFO.

Figure 9. RAM Module Creation Wizard

Conclusion: