An Emerging Solution For Embedded System Design

By Chris Balough, Triscend Corporation ( chris@triscend.com)

General-purpose microprocessors and microcontrollers have long been mainstays in embedded system design. In order to meet the unique requirements of a given application, custom or semi-custom logic devices, such as programmable logic devices or gate arrays, are found alongside the processor in many embedded systems. Recent advances in IC architecture, process technology, and software tools have led to the integration of an industry-standard processor core, user-programmable logic, memory, and a system bus on a single device. The resulting Configurable Processors utilize the programmable logic portion of the device to implement custom peripherals, allowing designers to easily and quickly create a version of that processor customized for a given application. Such Configurable Processors are targeted for embedded system applications that demand fast time-to-market without sacrificing product differentiation.

Embedded System Design
An embedded system is broadly defined as an electronic system that includes a microprocessor or microcontroller (i.e., the "embedded processor") that performs an application-specific set of functions. Embedded systems can be found in a wide variety of data processing, communications, industrial, automotive, and consumer equipment. Examples of embedded systems include the control circuitry in applications ranging from anti-lock brakes to missile guidance systems, from cable modems to central office switches, and from microwave ovens to electron microscopes. In many ways, the embedded system market is actually a broad array of market segments, with widely varying system requirements.

Design considerations are shifting
Embedded system implementation choices typically are driven by four considerations: time-to-market, competitive differentiation, performance, and cost. These goals often conflict with each other, forcing trade-offs between the various factors. As the market for embedded systems grows in size and in global reach, the resulting competitive pressures are reshaping how these trade-offs are balanced. Achieving performance and costs goals remains an important consideration in product design. However, the intense competitive pressures of the global market have added a new emphasis to the need for rapid time-to-market and effective product differentiation.

Time-to-market is the time required to define, develop, test, manufacture, and deliver a product to the end customer. Technological advances, constantly evolving standards, and increasing numbers of competitors have combined to shorten product life cycles - in some cases, to just a few months. As a result, getting new products to market quickly has become a necessary ingredient for success. Leading system manufacturers continue to accelerate their product development cycles in response to this need. Laggards pay a high price; market research clearly shows a direct correlation between getting a product to market early and the revenue and profits derived from that product.

Shorter product lifetimes and the resultant need for rapid design cycles are changing the way embedded systems are designed. To minimize design time and risk, products tend to be evolutionary in nature; the next product is likely to be a derivative of a current design, as opposed to a whole new approach. Thus, technologies that provide a high degree of flexibility and tolerance to change, such as user-programmable logic, have become increasingly prevalent. Furthermore, designers are focusing on their specific areas of expertise - that is, the application-specific portions of their systems - and are more likely to import other portions of the system from a previous design or an outside source (for example, purchasing the design of a processor core or peripheral from an intellectual property [IP] provider).

However, just getting to the market earlier than competitors is not enough to guarantee success; having the right product, of course, is as important as having it at the right time. To gain attention in an increasingly crowded and fast-paced marketplace, system manufacturers need to distinguish their products from those of their competitors. While cost, performance, and time-to-market can all be significant distinguishing factors, product differentiation is best achieved by providing a mix of functionality and ease-of-use that addresses the needs of the target market better than competitive products. The choice of technology plays a major role; for example, the use of only industry-standard processors offers product differentiation through software alone.

Technology alternatives
Today's embedded system designer has a rich choice of implementation options. Table 1 lists the advantages and disadvantages of several popular approaches to embedded system design, in terms of relative time-to-market (TTM), cost, performance (PERF), and product differentiation capabilities (DIFF).

Stand-alone processor:
A single MPU or MCU often is sufficient for simple designs. Using a popular, industry-standard device combines low component cost with an abundance of support tools and software. However, product differentiation is weak, accomplished via software only. Furthermore, the designer is limited to those architectures that are readily available on the market.

Processor derivative:
Processor derivatives offer the benefits of higher integration, as compared to a processor with discrete peripherals, but have many of the same advantages and disadvantages of the stand-alone processor. However, derivatives typically have weaker software support. Users of small-volume derivatives may experience availability problems and rising component costs. Furthermore, while offering varying mixes of peripheral devices, derivatives do not address other possible standard-part shortcomings, such as I/O pin constraints, memory limitations, or interrupt signal limitations.

Click to link to the full-sized table.

Processor with ASIC support logic:
Very high-volume applications can integrate peripheral functions into a single ASIC � typically a gate array. This solution offers high product differentiation, potentially high performance, and low component costs in high-volume manufacturing. However, these benefits come at the expense of longer design cycles and greater design risk. ASIC design cycles typically require extensive design simulation and test vector generation. Manufacturing turn-around times may extend the prototype/test cycle. These factors, coupled with IP licensing and transaction costs, mask generation expenses, EDA tool expenses, and ASIC minimum volume requirements, render this solution as economically infeasible for all but very high-volume applications.

Processor with PLD support logic:
This popular option provides many of the benefits of the Processor + ASIC solution, although with lower performance and higher component costs. Time-to-market and design risk are reduced compared to the ASIC solution, since PLDs (PALs�, CPLDs and FPGAs) are standard, user-programmable devices. However, significant effort is involved in integrating the two devices. The designer usually must duplicate the bus structure of the processor within the programmable device, often using a significant amount of the programmable device's resources. System-level debugging can be difficult, especially in terms of co-simulating and co-verifying the processor and PLD. Furthermore, overall system performance may be compromised by the I/O delays associated with communication between the processor and the programmable device.

Custom processor derivative:
The ever-increasing performance and density of gate arrays and FPGAs have prompted some adventurous designers to use these devices to create their own, customized processor integrated with all its peripheral functions in a single chip. This tight integration can result in significant performance advantages, as well as providing a very high degree of product differentiation. However, such a custom solution presents very significant design challenges. The designer must create the entire processor architecture and system bus structure, or, alternatively, purchase and interface to a core design obtained from an intellectual property (IP) provider. Basic software tools such as assemblers, compilers, and debuggers are weak, if they exist at all. System verification can be a long and difficult process. Of course, a standard processor (such as a subset of an 8051 MCU) can be implemented, but at an extreme cost compared to the readily-available standard device.

Embedded array:
To gain the advantages of high integration and avoid the difficulties of custom processor development, some high-volume, high-performance applications employ "embedded arrays". These devices combine a processor core and a semi-custom gate array on a single device. However, the development of embedded arrays involves many of the same difficulties, risks, and time-to-market delays of a regular ASIC, compounded by the issues incurred from embedding the processor core�processor tool compatibility and processor function verification. Like the standard gate array, embedded arrays are economically feasible only at very high volumes.

In summary, while a number of powerful technologies are available for embedded system design, each of these options can fall short of the growing need for both fast time-to-market and product differentiation.

The Configurable Processor Solution
The Configurable Processor represents an important advancement for embedded system design. A Configurable Processor is a single-chip combination of a microprocessor or microcontroller, programmable logic, memory, and a dedicated system bus. The programmable logic can be used to create custom peripheral functions, allowing for the rapid creation of customized processor derivatives. The user-programmable nature of Configurable Processors accelerates system design, thereby minimizing time-to-market, while its adaptability to custom designs allows for a high degree of product differentiation.

In many ways, Configurable Processors are the next logical step in the evolution of highly-integrated embedded system component technology. Microcontrollers combine processor and peripheral functions on a single chip, but allow little product differentiation. A single gate array or large programmable logic device can hold multiple custom peripherals, but must be interfaced to a separate processor. Including the gate array or programmable logic on a single-chip with the processor represents the next integration step, allowing product differentiation in a single-chip solution. The programmable-logic-based Configurable Processor is more effective than the gate-array-based embedded array in applications where fast time-to-market is imperative or production volumes do not justify a gate array solution.

However, it would be a misconception to view the Configurable Processor as just 'a processor with some programmable logic around it'. The user-programmable portion of a Configurable Processor is optimized to facilitate the creation of custom peripherals that operate with the on-chip processor in a system-level environment. Thus, the Configurable Processor's logic cells are significantly different than the logic cell structures found in standard CPLD and FPGA devices. Dedicated structures within the matrix of programmable logic resources provide system-level functions such as interfaces to the processor bus, address decoders, bus arbitration controls, data pipelines, and debugging facilities. Hence, the Configurable Processor should be thought of as an adaptable single-chip processor whose peripheral functions can be customized in hardware by the user, facilitating the creation of custom processor derivatives. The Configurable Processor's development tools reflect this conceptual view of the device architecture.

Configurable Processors are highly-integrated devices capable of incorporating most, if not all, of an embedded system's logic. The basic functions included within a Configurable Processor are shown in Figure 2 and described below:

Figure 1. Basic Elements of a Configurable Processor

A silicon-efficient, dedicated microprocessor or microcontroller provides the processing power of the Configurable Processor. Incorporating industry-standard processor cores within Configurable Processors allows the use of readily-available, third-party tools for developing and debugging the processor's code.

If a standard microcontroller (such as the 8051 controller) is implemented within the Configurable Processor, the dedicated peripherals normally associated with that controller (e.g., UARTs or timer/ counters) are also included in the Configurable Processor.

Configurable Processors include an on-chip memory capable of storing both system code and data. A small, bootstrap ROM supports system boot-up. Interfaces to external memory also are provided.

An area of programmable logic provides the logic resources for the creation of the custom peripherals or other user-defined functions.

System-level design is supported by additional test and control logic, such as JTAG interfaces, clock generation, power-on reset, and bus arbitration controls.

A dedicated, high-performance internal bus provides high-bandwidth communication between the processor and its peripherals, including the customized peripherals created in the Configurable System Logic.

Configurable Processors typically include an abundant number of programmable I/O pins, many more than commonly found on standard microcontrollers.

Since Configurable Processors include user-programmable logic resources, the complete "Configurable Processor solution" is a combination of both the Configurable Processor device and its companion development system tools. The development system allows for the rapid implementation of processor derivatives. Typically, this involves using a graphical interface and a library of "soft", parameterized peripheral functions to "drag and drop" the required peripheral functions into the design. Thus, the user would select from an on-line IP (intellectual property) library to define the functions to be implemented in the Configurable Processor, then immediately move to familiar, third-party software development tools to create, simulate, and debug the microprocessor program. In addition to accessing a library of pre-existing soft peripherals, users have the flexibility to use third-party EDA tools to create library entries of their own custom peripheral logic.

Configurable Processor benefits
The Configurable Processor combines many of the best aspects of microprocessors with those of programmable logic. Basing a Configurable Processor on a popular, widely-used microprocessor or microcontroller core takes advantage of the breadth of third-party tool offerings that support the use of that processor architecture, as well as the wealth of knowledge and experience with that processor within the embedded design community. The user-programmable nature of Configurable Processors adds the flexibility, adaptability, and fast time-to-market advantages that have fueled the rapid growth of the CPLD/FPGA market. Table 2 briefly lists some of the attributes of Configurable Processors in the same format as used in Table 1.

Table 2: Configurable Processor Attributes

Technology TTM DIFF PERF COST PROS CONS

Configurable Processor Excellent Excl. Excl. Good Fast time-to-market; High differentiation; Increased I/O; Strong software support; System debugging support; Architectural flexibility; Good cost in moderate volumes Processor-
centric solution; Moderately complex design

Configurable Processors offer much greater capabilities for product differentiation than commercially-available, stand-alone microprocessors or derivatives. User-defined functions can be implemented directly in hardware within the Configurable Processor, allowing the creation of a processor specifically customized for the given application. Furthermore, the Configurable Processor can circumvent many of the limitations of the native standard processor through features such as larger on-chip memory arrays, a multiplicity of programmable I/O pins, and expanded processor address spaces.

Configurable Processors also offer several advantages over multi-chip solutions featuring a standard microprocessor and an ASIC or programmable logic device. The Configurable Processor's dedicated bus improves system performance by eliminating the I/O delays of the multi-chip solution. Design cycles are shorter and easier since the user does not need to duplicate the bus structure within a separate device (the gate array, CPLD, or FPGA); in fact, the user does not even need to consider the details of the Configurable Processor's internal architecture. Debugging aids incorporated into the Configurable Processor facilitate system-level verification; no such structures are provided in the two-chip solution. Furthermore, the single-chip solution delivers the well-understood benefits of higher integration levels, including lower overall component costs and reduced circuit board size, power consumption, and EMI emissions.

With Configurable Processors, design time and effort and time-to-market are greatly reduced, especially when compared to semi-custom solutions such as the MCU/gate array combination or a processor-based embedded array. With the user-programmable Configurable Processor, design changes can be made easily, downloaded to the target device, and tested within the target system. The extensive simulation and verification tasks associated with gate array technology are avoided. Moreover, a Configurable Processor can have both its peripheral logic and processor code upgraded in the field.

Enabling technologies
Several technology advances have contributed to the introduction of Configurable Processors as a new class of ICs, including advances in manufacturing process technology and IC architectures, and the emergence of the "intellectual property" industry.

Due to manufacturing process incompatibilities, early programmable logic technologies were poor candidates for integration with processors and similar control logic. In the early and mid-1980's, programmable logic devices were based on "floating gate" technologies such as EPROM and EEPROM; requiring extra processing steps, these processes were significantly more expensive than standard logic processes, and building significant amounts of standard logic with these processes was not economically feasible. With the advent of SRAM-based FPGAs in the late 1980s and 1990s, a programmable logic technology that was process-compatible with microprocessors and similar logic chips emerged. However, the relationship between die size and manufacturing costs is exponential. At IC geometries of about 0.5 microns or larger, no economic incentive existed for creating a chip large enough to hold a powerful processor, all the needed support logic, and a substantial amount of user-programmable logic. (In other words, two medium-sized die were still much less costly than one large one.) However, recent advances in deep sub-micron process technology has lowered this barrier, allowing for the creation of the cost-effective processor/programmable logic combination found in Configurable Processors. The industry's first Configurable Processors are based on a .35 micron, 4LM process technology. Process technology advancements have paved the way for progress in the state-of-the-art in IC device architectures. For example, as improving process technologies have enabled higher integration levels, microprocessor capabilities and performance levels have been enhanced by adding features such as wider address and data busses, instruction pipelines, cache memory controls, and on-chip peripherals. The architecture of Configurable Processors draws on these past advances in the architecture of microprocessors and microcontrollers, as well as those of programmable logic devices and component interconnect schemes. The maturation of SRAM-based programmable logic technology (including the vast array of EDA tools and intellectual property products that support programmable logic design) and its acceptance in the design community were a pre-cursor to the development of Configurable Processors.

Another important contributor to the emergence of the Configurable Processor is the evolution of the intellectual property (IP) industry. As noted earlier, increasing system complexity, combined with time-to-market and product differentiation needs, have placed a high premium on design re-use; that is, the use of previously designed and verified portions of a system within new designs. One response to this need has been the growth and acceptance of the marketing of electronic designs as intellectual property, and the creation of an infrastructure to support this activity. A key component of that infrastructure has been the solidification of EDA interchange standards and design description languages such as EDIF, VERILOG, and VHDL, and the advances in logic synthesis technology that allow high-level descriptions to be transformed into working physical implementations. This continued development of the IP industry contributes to Configurable Processor technology in two ways: (1) an increasing number of popular microprocessors and microcontrollers available as IP cores enables the rapid expansion of Configurable Processors based on these cores, and (2) an infrastructure exists to support the third-party development and marketing of soft peripherals that support embedded system design using Configurable Processors.

Triscend Configurable Processor Technology Overview
The first Configurable Processors have been introduced by Triscend Corporation. These components, called Configurable Processing System Units (CPSUs), feature industry-standard processor cores, SRAM-based programmable logic cells, memory and a processor-independent, high-bandwidth system interconnect bus.

Basing CPSUs on popular processor architectures leverages existing development tools and code libraries. In addition, upward-compatible improvements to the processor can be incorporated when developing the core processor for a CPSU (for example, adding wait state capability to the bus of an 8051-based microcontroller). Furthermore, to facilitate the implementation of an entire embedded system, vital control logic accompanies the processor on the CPSU, such as clock generation and power management circuitry.

The matrix of programmable logic cells in a CPSU is referred to as the Configurable System Logic (CSL) matrix. The CSL matrix contains logic cells that can be configured to build almost any digital function. The CSL matrix is well-connected to the system bus, and is ideal for creating peripherals and other support circuitry for the microcontroller. The logic cell includes both combinatorial and sequential elements, and is capable of implementing a wide variety of logic, arithmetic, and memory functions. The configuration of the logic cells is controlled by SRAM memory; a configuration program is loaded into these SRAM cells during system initialization. Various configuration modes support different application requirements. There is no limitation to the number of times a device can be programmed, allowing for the rapid development and testing of design iterations. Dedicated logic associated with the CSL matrix provides needed system functionality such as system bus interfacing, data pipelining, and bus arbitration. Dedicated breakpoint management logic supports real-time, processor-synchronized debugging of the system.

Configurable System Interconnect Bus
The Configurable System Interconnect bus (CSI bus), the on-chip system interconnect bus within the CPSU, provides tight integration between the processor and the user-defined peripherals implemented in the CSL matrix. The CSI bus protocol is straightforward, and the bus is extensible in order to accommodate different processors and varying CSL matrix sizes. Conceptually, the CSI bus has three primary subdivisions: control and monitoring , the information path, and the CSI "Socket" (Figure 3). CSI bus control and monitoring signals provide for functions such as round-robin bus arbitration among multiple bus masters, wait-state control, breakpoint control, address decoding for dedicated peripherals, and external memory interfaces. The bus information path includes separate address, data read, and data write signal paths. The CSI Socket defines a simple synchronous interface to the "soft" peripherals implemented in the CSL matrix.

Figure 2. Primary Subdivisions of the Configurable System Interconnect (CSI) Bus

The control and monitoring signals and the information path are processor dependent, but the CSI Socket is processor independent. In other words, the CSI Socket is a processor-independent, open-system interface between the CSI bus and the programmable logic within a CPSU. It defines both the physical signaling interface between the CSI bus and the CSL matrix and the communication protocol between soft peripherals and the CSI bus. Once a peripheral function is created and implemented in the CSL matrix, it is portable across all Triscend CPSU product families (or other CSI Socket compliant devices), regardless of the architecture of the core processor. The CSI Socket is openly-documented, allowing both users and third-party IP providers to create additional libraries of "soft" peripherals that can be implemented within the CSL matrix of any Triscend CPSU.

As illustrated in Figure 4, the CSI Socket specifies physical signaling for address and data paths, clock and control signals, and the address selectors. The address selectors are built-in programmable address decoders that provide "chip select" signals for the various peripherals implemented in the CSL matrix; the use of this dedicated circuitry increases performance, as well as eliminating the need to use CSL matrix resources to decode bus transactions. Furthermore, the Triscend CPSU development tools use the address mapping capabilities provided in the address selectors to map the symbolic name for an address or address range within a given address space, as defined in the application software, to the appropriate physical locations within the CPSU. The logical addresses are defined and specified in an automatically-generated header file, which is added to the user's application code. Thus, existing code written for a given processor can be easily ported to a CPSU containing that same processor core, and available third-party development tools can be used to generate, simulate, and debug CPSU program code.

Figure 3. The CSI Bus Socket

The E5 family of CPSUs
The E5 family of Configurable Processor System Units hold the distinction of being the industry's first family of Configurable Processors. Each member of the family is based on an identical 8-bit microcontroller and a set of dedicated resources (Figure 5). However, the larger members of the family include more system RAM, additional programmable I/O pins, and a larger CSL matrix, as detailed in Table 3. Family members that share a given package type also share a common footprint in that package, allowing designs to migrate among the family members without modifying the printed circuit board.

table 3

Figure 4. E5 Configurable Processor Block Diagram

The E5 family is based on an enhanced version of the popular 8-bit 8032 microcontroller. (The 8032 microcontroller is an enhancement of the 8051 device.) E5 CPSUs are fully binary and source code compatible with other industry-standard 8032 and 8052 devices. However, the "turbo" 8032 microcontroller in the E5 CPSU offers several significant improvements over the standard 8032 device:

The E5 CPSU's instruction cycle is only four clock cycles long, versus twelve for the original 8032 microcontroller, yielding enhanced performance at the same clock frequency, and providing up to 10 MIPs performance at 40 MHz.
The E5 version includes a second, additional data pointer, easing data transfer routines.
Programmable wait state capability facilitates interfacing to slower memory or peripheral devices.
Power management control provides selectable power-down options for internal functions.
There are several optional sources for the clock, including an external clock, external crystal, or on-chip ring oscillator. Optionally, the bus clock can be stopped upon a breakpoint event.
On-chip power-on reset circuitry eliminates the need for an external resistor-capacitor network.
Due to the presence of additional features and peripherals, the number of interrupt sources and vectors is increased.
Address mapping logic translates the 8032 MCU's 16-bit address to the 32-bit physical address used by the CSI bus.

Several dedicated resources are integrated into the microcontroller of the E5 CPSU. The CPSU includes a dedicated serial I/O port and three 16-bit counter/timers, just as in the original 8032 device. In addition, E5 resources include an additional watchdog timer, a two-channel DMA controller, up to 315 I/Os (depending on the size of the CPSU), up to 64 Kbytes of RAM, a small initialization boot ROM, an external memory interface, JTAG port, breakpoint control logic, and, of course, the CSL matrix. The Configurable System Interconnect bus in the E5 CPSU includes a 32-bit address bus and 8-bit data busses, and can support up to 40 Mbyte/sec transfer rates. Together, this wealth of resources can be used to create powerful, highly-integrated, flexible systems.

Configurable Processor Software - Creating a "Derivative-on-Demand"
E5 CPSU design is supported by the Triscend FastChip� Configurable Processor Development System. The FastChip system manages CPSU device configuration and oversees the entire development flow. With this highly-graphical, Windows�-based software, embedded system designers can quickly create custom 8032 microcontroller derivatives "on demand" using a library of parameterized, pre-engineered, and pre-licensed functional modules. Users can also create their own custom peripheral logic using popular third-party schematic capture and logic synthesis tools.

Figure 5. "Derivative on Demand" Design Flow

This Configurable Processor "Derivative-on-Demand" development flow, outlined in Figure 6, is almost identical to the development flow for a standard "catalog" processor derivative. In 4 steps, the designer progresses from idea to a production-ready solution

Step 1--"Drag and Drop" Configuration:
Starting at the FastChip system's configuration interface (shown in Figure 7), the designer decides which peripherals are necessary for the embedded system. From the library of pre-existing soft peripherals, the designer then "drags and drops" the desired peripherals into the CSL area. As each soft peripheral is added, graphical gauges provide the user with dynamic feedback on the amount of CSL resources that remain. The FastChip development system includes many soft peripheral modules, yet the user can also create custom peripheral logic using standard schematic capture or logic synthesis tools.

Figure 6. FastChip Development System's Configuration Interface

After the modules are "dragged and dropped", graphical interfaces are then used to select the parameterized options for each function (for example, timer/counter options would include operating mode, clock source, and initial value). This graphical parameterization is also available for the dedicated functions, such as the 8032's native time/counters.

After all the soft peripherals are designated and the parameterization is complete, the FastChip software automatically produces a "header file" that assigns logical addresses and symbolic names for the registers in the CPSU's soft peripherals. This header file will be included in the processor application code to assist with the application code development. The designer does have the option to override the automated header creation and assign specific symbolic names and memory map locations.

Step 2--Processor Code Development:
With the header file created, the designer now invokes the standard processor code development tools to begin developing the processor code, which is typically created in "C" or "Assembly". The code for any application often re-uses code written for previous applications. At this step the developer will include the header file created in Step 1. This header file provides all symbolic naming and memory for the soft peripherals, such that the developer can treat these functions as if they were dedicated device functions. The developer is spared from needing any knowledge of how the soft peripherals are implemented. After the code development is complete, the finished code is then compiled (or assembled) into object code.

Step 3--Processor Code Simulation:
After code creation, the designer must now begin to verify its functionality. The first phase of this verification is typically logical verification, which requires the developer to establish a simulation test plan to be sure the basic code function is as intended. For embedded systems, which often face real-world signal conditions that are difficult to predict, this simulation stage will frequently omit I/O simulation, leaving that to in-system testing.

After the designer has reached the point of satisfactory logic code simulation, FastChip software will now create a configuration file for the CSL matrix, then merge that with the processor's object code to create a single data image. This image is then downloaded to the CPSU's external memory through its JTAG interface, or the image can be programmed into a non-volatile memory using a standard memory programmer.

Step 4--System De-Bugging and Verification:
The stage is now set for exhaustive system verification. At this point, the designer will have the CPSU in its target application running at-speed. For testing purposes, this system is often housed in an environmental chamber to provide worst-case operating situations. The CPSU will be connected to a PC for debug monitoring and runtime control. During this step the FastChip software acts as an intermediary to the designer's customary debugging tool. The debugging tool's communication commands are translated by the FastChip software to the JTAG commands that control the CPSU's hardware breakpoint unit. This allows the designer to completely control and monitor the CPSU's performance--such as managing breakpoint events and examining internal register contents--using a familiar real-time debugger interface. Designer inquires about the status of addressable soft peripheral registers are handled as command-line inputs, using the symbolic names of the registers.

In some situations, a designer may wish to perform more advanced debugging that interrogates the interior status of the CSL matrix. FastChip software provides a debugging utility for designers who desire to delve into this detail. Triscend's CPSU devices provide for the observability and control of each logical and combinatorial node in the CSL matrix, so designers can mix processor debugging techniques with logic debugging.

Key Observations:
The Configurable Processor is designed such that the designer can create a project using this technology in the same manner, and with the same tools, as if it were a standard "catalog" derivative. This "derivative-on-demand" design flow insulates the developer from the details of the programmable logic, so that the code development techniques and tools are the same.

CPSU extensibility and technology roadmap
The architecture of the Triscend Configurable Processing System Unit is extensible, both in terms of creating future CPSU devices and expanding the library of pre-engineered functions available for creating microcontroller derivatives-on-demand. The CPSU architecture was specifically designed to allow for the inclusion of various types of core processors while allowing other elements of the architecture and the development software to remain essentially unchanged. The turbo 8032 microcontroller was chosen for the first CPSU implementation due to its relative simplicity, popularity among embedded designers, and wealth of third-party tool support. Future CPSU families will feature more powerful general-purpose processors, such as 32-bit RISC and CISC processors, as well as more specialized processing architectures, such as digital signal processors. Of course, each CPSU device will be designed to be fully software-compatible with the standard version of the processor core, allowing the user to take advantage of existing software libraries and tools, including real-time operating system software.

While the CSI bus control structures and information paths can be modified to accommodate varying processor architectures, the CSI Socket interface will be identical throughout the entire range of Triscend CPSU devices. This guarantees that soft peripherals - from Triscend or created by users - will be forward-compatible with future CPSU families. Triscend will continue to expand the library of available modules for its CPSU devices; while the initial version of the FastChip system includes many common peripheral functions such as counter/timers, serial I/O ports, and interrupt controllers, future releases will include larger modules such as CAN interfaces, USB ports, Utopia interfaces, and DSP functions. Third-party IP providers can offer additional modules, and CPSU users also can create their own library entries.

The FastChip development system provides for the creation of new library modules using industry-standard EDA tools such as the OrCAD schematic editor and Synopsys logic synthesis tools for programmable logic. Future releases of the development system will expand these capabilities and support additional EDA tools. Thus, users with demanding applications that cannot be addressed with the currently-available libraries will be able to implement any desired custom logic in the CSL matrix using standard ASIC-like design tools and methodologies.

Since Triscend CPSU devices are fabricated on an industry-standard CMOS IC manufacturing process, dramatic cost reductions can be reliably predicted based on process improvements and shrinking process geometries. Planned migrations to .25 and .18 micron technologies over the next five years will result in cost reductions of up to 75% compared to current manufacturing costs. Process migration also will lead to higher performance and higher integration levels for CPSU devices.

Summary
Configurable Processors represent a new generation of microprocessor technology wherein the processor's peripheral logic can be modified to match the needs of each unique application. By integrating an industry-standard microprocessor with flexible user-programmable logic, memory, and a high-bandwidth system bus on a single device, Configurable Processors provide an ideal solution for embedded system designs where time-to-market and customization are essential.

Triscend Corp. has developed the industry's first Configurable Processors, the E5 family of Configurable System Processing Units. The Triscend CPSU architecture is designed for processor portability and the interoperability of soft peripherals across multiple CPSU families.

The FastChip Configurable Processor Development System manages CPSU device configuration and provides for the easy creation of microcontroller derivatives-on-demand. It also provides seamless integration to third-party code development tools and supports the expansion of soft peripheral libraries. Thus, an embedded system designer can create a customized processor without needing detailed knowledge of the internal programmable logic technology, quickly complete design iterations with no limit on the number of iterations, and preserve existing processor development tools and software libraries throughout the development cycle.


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