FPGA Large Device Design Methodology

By Tom Hill, Exemplar Logic (tom.hill@exemplar.com)

(Editor's note ı The following is a summary of 50 page technical article that can be accessed at http://www.exemplar.com/edtn/methdology)

1998 saw the introduction of FPGA devices that exceeded the 100K gate barrier. In 1999 Xilinx, Altera, Lucent, Actel and Vantis will all provide devices in excess of several hundred thousand gates. Rather than implementing a simple function in an FPGA, designers will take advantage of the large gate counts to implement entire systems. Successfully designing these large devices will require engineers to seek new design methodologies and the tools to support those methodologies.

The Methodology Breakdown
Today's FPGA design methodology is characterized by its ease of use. Due to the small number of major FPGA vendors, EDA companies can afford to develop automation technology not available in comparable topdown ASIC design flows. This typically includes automatically inserting I/O buffers, reset circuitry and RAMs from RTL code. EDA vendors are beginning to encapsulate place and route software in their products. And timing constraints are often set as global values not specific to any port or module. Modest gate counts combined with built-in automation combine to create a synthesis process that is easy to learn and highly productive to use for small PLD devices.

With the arrival of programmable logic devices based on .35 and .25 um technology this simplistic approach to optimization begins to break down. Designers need to focus on these large chips one block at a time or as multi-engineer design teams. This facilitates the need for hierarchical design techniques and functionality. Scripting becomes a valuable tool for managing data and building designs. Users must set detailed constraints on each sub-block including loading, drive, clock period, input arrival time and output setup time. Large designs often require the use of more sophisticated timing constraints such as false path, multi-cycle paths and multi-clocks as well. Successful bottom-up design require programmable logic designers to borrow ASIC style design techniques and understand how they apply to the unique characteristics of SRAM based FPGAs.

Further complicating matters, intellectual property (IP) is gaining in popularity among FPGA designers as they seek to exploit the recent advancements in gate counts by implementing systems on their FPGAs. Depending on the provider, IP can be delivered in a variety of formats ranging form gate level netlists to RTL code. Synthesis tools need to offer a high degree of control over the results to successfully implement softcores. IP delivered as pre-optimized netlists must be incrementally read into a synthesis tool and incorporated into the top-level design. Incorporating IP forces designers to move beyond "push-button" synthesis into Large Device Design Methodology.

Large Device Design Methodology
Large Device Design Methodology requires tools that offer the power and flexibility to adapt to a broad range of unpredictable situations. Leonardo Spectrum is an advanced logic synthesis environment that can be customized using over 200 system variables. System commands can be used perform design partitioning, set timing constraints and addressing problem areas such as multi-cycle paths and false-paths. The technical details of performing bottom-up optimizations are discussed at length.

Large devices generally mean large amounts of design data. Special care must be taken to set up your design environment. This includes directory structures and script organization, both key elements of a successful design methodology. Common setups and tasks can be pre-defined in advance through alias and startup files.

A variety of optimization strategies exist for FPGA designers. If the design size is small a topdown methodology may provide simple approach to successful optimization. When gate counts become excessive, engineers generally decide to "divide and conquer" as either an individual working sub-block in sequence or by forming design teams. Bottom-up design requires engineers to make decisions on logic partitioning and calculate internal timing requirements. In depth knowledge synthesis technology may prove valuable when making these decisions. Users should decide up front how they want to optimize each block and leave only assembly of the subblocks as the last step or attempt a final "tuning" optimization. These are all issues discussed at length in FPGA Large Device Design Methodologies.


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