Fixed Granularity FPGA Architecture
The classic FPGA architecture, the "4LUT and a flip-flop" building block, is the foundation for many FPGA products. It consists of a 16-bit look-up table that can fully decode four inputs and a flip-flop to store the result. It may include embedded or distributed memory for additional flexibility. It is a simple architecture that is very efficient at what it does.

Applications that need four or fewer inputs are easily implemented in the fixed granularity architecture. While a four-input application makes the most efficient use of the building block, two- or three-input functions can be implemented with a 33% to 50% sacrifice of the LUT resource. Also, when an application calls for anything wider than four inputs, multiple four-input blocks may be cascaded to create whatever level of logic is needed.

On the plus side, the fixed-granularity 4LUT architecture is well known and makes efficient use of silicon. It scales easily to virtually any density. Because it is a simple architecture, the development software that supports it is also simple and can scale with the architecture.

On the other hand, cascading requires extensive use of general routing resources. As a result, performance suffers when 4LUT building blocks are cascaded to build the wide functions of the type required for CPLD applications. While process technology advances give this architecture better performance than it had in older technologies, it usually isn't enough of an increase to overcome the performance degradation caused by cascading. As a result, the fixed granularity architecture may prove unacceptable for integrating CPLD applications into an FPGA.

Mixed Logic FPGA Architecture
An obvious approach to integrating FPGA and CPLD applications on one chip is to put both FPGA and CPLD architectures on one chip. For example, mix classic FPGA 4LUT-plus-flip-flop building blocks with CPLD sum-of-products structures on a single chip. Embedded memory may be included for additional flexibility. This approach allows data-path types of applications to be assigned to the FPGA building blocks and control or state-machine applications to be assigned to the CPLD structures.

In this approach, both CPLD structures and FPGA architectures share a global, hierarchical FPGA-like interconnect structure for inputs and outputs. A control function implemented in a CPLD structure may receive its inputs from FPGA-based functions elsewhere in the FPGA, and may send its outputs to other FPGA or CPLD logic within the chip or directly to output pins. The global interconnect structure provides the lines of communications.

This approach has obvious advantages. It allows CPLD blocks to handle wide gating functions without cascading FPGA building blocks, thus improving performance within the local CPLD block. It also provides a level of predictability within the CPLD blocks that is not possible in classic FPGA architectures.

This approach has equally obvious, and in some cases not so obvious, disadvantages. The most obvious is that that the hierarchical FPGA-like interconnect structure dampens the performance of the CPLD blocks and decreases their predictability. An embedded CPLD cannot possibly match the performance of a stand-alone CPLD. For applications where this is not a serious problem, this class of FPGAs may be a good choice. For those applications where stand-alone CPLD performance is needed, stand-alone CPLDs will be used.

A less obvious disadvantage is that mixing different types of architectures on a single chip puts a heavy burden on logic synthesis and place-and-route software. Providing efficient synthesis or place-and-route support is complex enough when dealing with a single type of CPLD or FPGA logic. New software must be developed to support these new merged architectures, and simply joining CPLD place-and-route software with FPGA software in a single package will not solve the problem. For example, how does the software recognize CPLD functions and assign them to CPLD blocks while assigning FPGA functions to FPGA blocks? This isn't a problem for stand-alone CPLD or FPGA software because this decision is made by the system designer before submitting the design to the software. New HDL coding styles may be required to allow the system designer to direct assignments of various blocks of logic.

Perhaps the toughest problem for the FPGA/CPLD architecture designers is determining the ratio of FPGA logic blocks to CPLD logic blocks. Any ratio that you choose will be exactly right for a small percentage of designs, almost right for a somewhat larger percentage, and wrong for an even larger percentage. The result will be inefficient use of silicon for most designs.

When integrating CPLD and FPGA architectures on a single chip, it's most likely that all the logic blocks in the integrated architecture chip will use volatile, SRAM-based internal configuration memories. To do otherwise would limit the device to being manufactured in a process technology that implements non-volatile memory cells. This should not be a problem for most CPLD applications, except for those applications where the function must be operational immediately on system power up. In those cases, stand-alone CPLDs will be used.

Variable Granularity FPGA Logic
The third approach to CPLD/FPGA integration, variable granularity FPGA, attempts to address the inherent disadvantages of both the classical and the mixed-architecture approaches. Rather than using a classical FPGA architecture or mixing classical FPGA with classical CPLD architectures, this approach creates a new architecture that addresses both CPLD and FPGA applications.

Specifically, variable granularity allows both wide- and narrow-gating functions to be implemented using the same logic without cascading. In the Vantis VF1 FPGA architecture, for example, the lowest level building block is a 3LUT, with two 3LUTs sharing a single flip-flop. These two 3LUTs can be combined to create a classic 4LUT-plus-flip-flop architecture. But they can be combined even further to create 5LUT and 6LUT functions in a single level of logic, using only very high-performance multiplexers to establish the connections between them.

A variable-granularity architecture that targets CPLD applications must address more than six input functions. Preferably, thirty-two input-wide functions should be a minimum, with sixty-four being even better. The Vantis VF1 architecture cited above handles thirty-two inputs in two logic levels using only local interconnect. That is a step in the right direction, and proves the viability of variable-grain architectures in handling wide-gating functions without embedding CPLD architectures on the chip.

A key element in a variable-granularity architecture is the use of high-performance local interconnect in addition to hierarchical interconnect. Hierarchical interconnect lines typically add as much or more delay than logic blocks. The use of short, dedicated interconnect lines reduces this delay significantly, thus improving performance for both CPLD and FPGA functions.

The variable-grain architecture approach offers several advantages over both the classic FPGA architecture and the mixed-architecture approaches. First, it offers performance that is comparable to the mixed-architecture approach and higher than the classical FPGA cascaded approach. Because it uses only one type of architecture, it offers more efficient use of resources than the mixed-architecture approach, resulting in more efficient use of silicon in most applications.

Since variable-granularity architectures are more complex than classic FPGAs, development software will be more complex, but should not be as complex as that needed for mixed-architecture devices. Like the mixed-architecture devices, special HDL coding styles may be needed to extract the best possible performance.

Architecture characteristics comparisons for wide-gating functions

Architecture	Performance	Resource Usage	Software Complexity
Fixed grain	Moderate	Moderate	Low
Mixed logic	High	Low to moderate	High
Variable grain	High	High	Moderate

Conclusions
Clearly, advances in FPGA architecture will allow FPGAs to handle both narrow-gating data path and some wide-gating control functions as system functionality is integrated into fewer chips. But it's equally clear that mainstream CPLD functions (control functions that require high performance, high predictability, or non-volatile internal configuration memories) will remain in the CPLD domain.