IP'99 Conference Report

By Murray Disman (mdisman@chipcenter.com), Editor EDTN PLD Design Center

This was the third year for this conference on Intellectual Property (IP). Attendance at this meeting exceeded that at the first two and more than 40 companies exhibited at the show. The basic IP core industry and its role and relationship with the semiconductor design and fabrication companies is evolving and will certainly change over time. A number of independent industry organizations have been setup to deal with the various business and technical aspects of IP as it effects the OEMs, IP suppliers, ASIC vendors, traditional broadline semiconductor companies, fabless IC vendors, semiconductor fabs, PLD suppliers, and EDA tool companies. In fact, as the trends and impact of IP use begins to unfold, it is apparent that it will effect the operation and structure of the entire electronics industry.

IP, as covered by the meeting, is also called virtual components, cores, modules, etc. These are electronic circuits/functions that can be used by parties in addition to the one that did the initial design. The conference covered a broad range of business, technical, and commercial topics related to IP. Even though there were some discussions concerning the relationship between IP and FPGAs, the major emphasis at the meeting was on the use of IP in the design and fabrication of ASICs.

The driving forces behind the move to IP are the same ones that have been dominating OEM thinking for some time. These are to reduce the time-to-market for new and modified designs and to reduce the size, weight, power consumption, and cost of their products. Two key factors that have and will influence time-to-market are the use of PLDs to construct prototypes to allow the simultaneous development of the hardware and software and the use/reuse of IP cores to reduce design time.

The use and reuse of IP cores is being put forth as the way to close the gap that has developed between the ability to design complex systems and the ability to fabricate these on a single device. The rapid migration of process technologies to finer geometries has resulted in a situation where device capacity now exceeds the design capabilities of most OEMs. One way out of this difficulty is to design at a much higher level, a level that relies on the use and reuse of large blocks of circuitry (IP cores). The reuse of previous proven designs by the OEM is a key element in closing the design gap. Third-party IP cores will increase in importance for the OEM, with time.

One trend that is occurring in this move to a "system-on-a-chip" or system level integration is the use of on-chip bus architectures. These are being used to interconnect and separate the IP blocks that constitute the design. The separation of the blocks is being done to simplify IP core checking both during the design verification and debugging phase and for testing after implementation. It seems that the bus approach is not the most efficient technique in terms of silicon usage and that it also places some limits on system performance. The higher volume chips, such as those going into cell phones, video games, and set top boxes, will probably not use internal bus structures.

Defining IP Cores
The variations in the terminology used to describe IP cores seem to be settling down as this area matures. There are a number of different techniques that can be used to categorize IP cores. The technique chosen depends on the reason for the exercise. Two good methods that aid in understanding the structure of the industry and in identifying trends are to categorize the core by their structure when delivered and by their value/complexity.

Another useful method is to categorize cores by the application area being served. The independent IP companies tend to develop expertise and to work in specific application areas. Typical application areas include interface circuits, microprocessors, memory, microcontrollers, DSP cores, DSP functions, error correction, encryption/decryption, data communications, control, etc.

Cores are often distinguished by their structure. The most common categories are;

Soft cores - These cores are written in HDL code, either VHDL or Verilog, which can be synthesized into a supplier's ASIC or PLD library. These cores do not contain coding that restricts the target technology.

Firm cores - Firm cores can be in HDL or netlist formats and contain information concerning the target technology. One such example is the 66MHz/64-bit PCI interface cores from Altera and Xilinx. These cores contain placement restrictions for the high performance parts of the circuit. Another example of a firm core is Dolphin's 8051 core for Xilinx's Virtex devices that is delivered as an EDIF netlist.

Hard cores - These cores are defined in terms of a specific semiconductor fabrication process and are typically delivered in the form of GDSII mask data. The ARM and MIPS processor cores are examples of hard IP cores.

There was a general consensus that value of an IP core was related to its complexity. While this may be usually true, memory cores are usually not complex but can be very valuable. Rambus is such an example.

A better definition was offered by Synopsys, which segmented IP cores by IP value and differentiation. Differentiation is the degree by which the IP core is different from others offered by competitors. Differentiation could be equated to value since those with highly differentiated cores can charge higher prices. But, differentiation can also be achieved with patents, industry acceptance, availability of specialize supporting software, etc.

Synopsys divides the IP core universe into three areas. These are;

Building block libraries
Complex IP cores
Star IP

Building-block libraries are a basic collection of pre-designed gates, flip-flops, adders, multipliers, etc. Generic or building block libraries had their start with the basic TTL libraries and have continually grown in complexity. It is not unusual to find libraries that contain relatively complex parameterizable functions. In fact, the line between libraries and commodity IP cores is blurred in that some companies include modules in their libraries that other companies are trying to sell as IP cores.

These libraries are usually included with the design tools supplied by PLD, ASIC, and synthesis companies. Each library is unique to a specific process. DesignWare, delivered with Design Compiler, from Synopsys is one of most widely used libraries with some 8,000 users.

Complex IP cores comprise the area that is most heavily populated with both established and startup companies. Many of these companies began as design houses, but saw an opportunity to leverage their knowledge and skills into a "standard product". Most of these organizations were not prepared for the level of support and the quality of product needed to succeed. In addition to consulting support for the customer, is necessary to supply models, test benches, boards with the implemented IP, simulation vectors, etc.

Complex or commodity IP cores are typically based on implementing standard bus interfaces such as PCI, 1394, or USB or standard microcontrollers/microprocessors. However, there are very complex offerings such as MPEG coders/decoders, encryption/decryption, and error encoding/correction cores that intrinsically have more value and offer greater opportunities for differentiation.

Synopsys has decided to increase the scope of DesignWare and to start including complex IP cores at no additional cost to the customer. The first three cores to be included in DesignWare are a 16550 UART, an 8051 microcontroller, and a 2.2-compliant 66MHz/64-bit PCI interface core. This move will clearly have an impact on the complex/commodity IP core vendors, especially those delivering products at the lower end of the complexity spectrum.

Star IP is where the money is today. This area contains the offerings from ARM, MIPS, and Rambus, which have all developed successful business models. Also included in the Star IP area are the designs that have been previously used by the OEM. The reuse of previous implemented and verified designs by the same OEM is currently the most important use of IP cores. One difficulty that arises is much of this in-house IP has not constructed with the idea of reuse. There are now numerous guides and tools to aid the OEM in building an IP core library for reuse.

Programmable Logic and IP Cores
While the primary emphasis at the conference was on the use of IP cores with ASICs, there were some discussions and papers concerning the role of FPGAs in the use of IP cores. Altera and Xilinx presented papers about different aspects of core use in PLDs. Two panels discussed the use of IP cores in FPGAs.

The general feeling was that the cause of the slow acceptance of IP cores by FPGA designers was primarily due to the small capacity of the devices that had been available. FPGA are now being shipped with several hundred thousand usable gates and these larger devices can accommodate the more complex cores. The consensus (or hope) was that the larger FPGAs and the growing trend in the use of FPGAs to prototype ASICs would insure a growing use of IP cores with FPGAs.

Synplicity's announcement of the extension of its Strategic Access Partner Program to include leading IP vendors is indicative of confidence in this trend. Their goal is to provide optimized synthesis support for complex FPGA designs. The six charter IP members, Cast, Comit, CoreEl Microsystems Inc., Lexra, Memec Design Services and PLD Applications, will each develop and verify a new timing model for their IP cores for use with Synplicity's Synplify synthesis tool. It is anticipated that Synplify users will achieve significantly better overall design optimization when using this timing information within the IP core.

There is some confusion about what to call the special functions that are embedded in the same silicon chip as an FPGA. This is a trend that is still in its infancy. Programmable products have been announced with embedded PCI interfaces and embedded processors. Some of the vendors refer to these as hard cores, which they certainly were at point of defining the mask sets for the function. I feel it would be more appropriate to call these embedded functions, once they are on the chip with the FPGA, and to call the overall product an application-specific programmable product (ASPP).

Some of the vendors are also beginning to refer to these devices as standard products with embedded sections of programmable logic. In fact, there were considerable discussions during the conference about the utility of having a programmable logic core as part of a system-on-a-chip. This idea has been around for some time, but yet to surface in the market place. The closest is the Lucent Technology cell-based ASIC, which includes a section of Chip Express's laser programmable gate array.

Synopsys has directly addressed FPGAs with embedded functions with the release of version 3.1 of FPGA Express and FPGA Compiler II. The company claims that its FPGA synthesis software is the first to support new programmable technologies such as field programmable system chips (FPSCs) from Lucent and configurable processors from Triscend. Version 3.1 enhances the Lucent FPSC core by automatically encapsulating detailed information about the PCI core and associated modules into the flow. According to Synopsys this significantly streamlines the design process, as designers do not need to manually enter this information.

In addition to the support for the FPGAs with embedded functions, version 3.1 includes enhancements that improve quality of results by automatically inferring architecture-specific mulitplexor functions. These multiplexor functions can result in improvements of up to 50 percent for both area and performance, depending on the amount of mulitplexing performed.


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