The high end of the FPGA spectrum, designs larger than 50,000 gates, can be characterized by high value added and much higher cost/usable gate. As gate counts increase beyond 100,000, the time to compile, silicon efficiency, cost per used gate, and design performance degrade significantly when compared to equivalent density gate arrays. To help deal with such complex designs, designers will inevitably come to rely on IP (Intellectual-Property) cores to implement large portions of their designs.

Figure 2

As designs continue to increase in gate count and complexity, there will be a split in the greater than 100K gate FPGA market. Designs will be implemented in "pure" FPGAs, and designs will be implemented in system level integration chips, where 80-90% of the logic will be "fixed", and 10-20% of the design will be programmable (FPGA). The benefits of this later approach are much faster compile times, significantly improved silicon efficiency, higher performance designs and much lower cost per gate. Essentially the user will get the combined benefits of gate array cost and speed with the flexibility and reduced design risk benefits of FPGAs.

This paper will introduce the concept of Field Programmable System Level Integration Circuits and associated design tools used to implement system level logic. The paper will present a new design approach with integrated FPGA, microcontroller, peripherals and SRAM. Issues such as architecture, concurrent hardware and software design will be addressed.

Atmel's newly introduced AT40K SRAM-based FPGAs, shown in figure 2, are uniquely qualified to handle the demands of the new era of IP cores and high-density logic design. Like other FPGA's, the AT40K has user-accessible RAM. But it is not relegated to the edge of the array, making RAM-based cores difficult to implement. Nor is it embedded in the logic cells, degrading performance and forcing a tradeoff between logic and RAM. The RAM is distributed throughout the array (where it's needed) with minimal impact on performance. The AT40K has logic resources and cell-to-cell connectivity optimized for high speed computing applications. Implementation of DSP cores is exceptionally efficient. The AT40K supports Cache Logic design; the ability to "hot swap" circuit modules in much the same way as software modules are swapped in software caching. Taken together, these features make the high-density AT40K FPGA ideally suited to implementing IP cores. In addition, the AT40K family has been designed with ability to be embedded into much larger, system-level devices, to create programmable system level integration (PSLI) devices.

The AT40K is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 475-pin BGA, and support 3V and 5V designs. A logical overview is shown in figure 3.

The AT40K is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC, Sun and HP platform. Atmel's design tools provide seamless integration with industry standard tools from Cadence (Concept/Verilog), Everest, Exemplar, Mentor, OrCAD, Synario, Synplicity, Veribest, and Viewlogic.

The AT40K can be used as a Coprocessor for high-speed (DSP/Processor-based) designs by implementing a variety of compute-intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications.

The AT40K FPGA offers a patented distributed 10ns SRAM capability (figure 4) where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool.

Figure 3

Figure 4

The AT40K's patented 8-sided core cell (figure 5) with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any bussing resources, as shown in figure 6.

Figure 5

The AT40K is only FPGA family capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40K can act as a reconfigurable coprocessor. The AT40K's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. Often times the partial products of a multiplier or the coefficients of a filter are stored in the look-up tables of the FPGA. These values may be stored in external configuration memory, and downloaded into the FPGA as required, as shown in figure 6. This can greatly increase flexibility while reducing FPGA size and cost. An example of this is in edge detection, where coefficients may change due to different lighting conditions. By utilizing Cache Logic design techniques, the FPGA can be partially reconfigured based on the lighting conditions detected. This concept may also be applied to echo cancellation in a wireless office switch, where new coefficients can be calculated on-the-fly, and downloaded to the FPGA as required.

The AT40K is the only FPGA family capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators (figure 7) work seamlessly with industry standard schematic and synthesis tools to create fast and efficient designs in a very short time. The FPGA design tools include a timing driven automatic place and router, conversion utilities from other FPGA vendors, architecture mapping, multi-chip partitioning, floor planning, and many other features, as shown in figure 8.

Figure 6

Figure 7

Figure 8

As the number of logic gates in a design increases, the nature of the design implementation requirements change as well. Typically, in a design less than 10,000 gates, the application is usually random logic in nature. The need for user SRAM is low and the number of I/Os is usually under 200. As the design increases in size, the logic usually becomes structured in nature, and user SRAM requirements increase. In designs under 10K gates, only about 10% require SRAM, while in designs larger than 25K gates, about 80% require some SRAM on-board.

The problem with using large FPGAs today is that they must be designed in much the same manner as lower density devices, that is using either schematic-based or behaviorial-based design techniques. Also, large FPGAs tend to consume a very high amount of power, have long cross-chip delays, take a very long time to compile, and cost significantly more per gate than their lower density cousins.

Figure 9 shows Atmel's FPGA roadmap for period of 1996 - 2000. Most FPGA vendors are showing similar roadmaps, where process technology is shrinking and gate counts increasing to over 1 million. As FPGAs reach 0.35u process, a new capability emerges; that of embedding the FPGA with other system level logic.

So the question becomes one of density, speed and cost. Typically, only 10-20% of a design requires configurability - the remainder of the logic is standard, off the shelf components. Due to the cost of programmable circuitry, a programmable solution will always be more expensive (larger) than a custom, ASIC solution. With the feasibility of embedding FPGA on ASIC silicon, it is now possible to have a programmable system level integration (PSLI) solution, as shown in Figure 10.

Figure 9

Figure 10

New families of FPGA-based system level integration are being developed with up to 1 million logic gates capacity. These devices include embedded microcontrollers, DSP, SRAM, peripherals and FPGA. The advantage of this approach is significantly lower cost, lower power, faster compile times and higher performance. This is due to the fact that speed critical logic can be built in ASIC and instead of the entire design being implemented in a larger, more expensive FPGA, only those gates that require configurability are implemented in FPGA.

Figure 11

Designers can choose from various size gate arrays and FPGAs, essentially "mixing and matching" as shown in figure 11, to meet their specific design requirements. Gate array options range from 50K to 500K gates, while FPGA options range from 10K to 80K gates. This approach offers designers access to a large offering of intellectual property (IP) in the area of network, telecommunication, multimedia, mass storage as shown figure 12. These devices can be manufactured on a number of advanced processes, including CMOS, BiCMOS and SiGe. These cell-based cores can be combined with embedded volatile or non-volatile memory, FPGA, DSP, Microprocessors, Bus interfaces, A/D, D/A converters, Codecs analog and RF to build truly reconfigurable system level integration devices such as those shown in figure 14.

Figure 12

Figure 13

Summary

The high end of the FPGA spectrum, designs larger than 50,000 gates, can be characterized by high value added and much higher cost/usable gate. As gate counts increase beyond 100,000, the time to compile, silicon efficiency, cost per used gate, and design performance degrade significantly when compared to equivalent density gate arrays. To help deal with such complex designs, designers will inevitably come to rely on IP (Intellectual-Property) cores to implement large portions of their designs.

As designs continue to increase in gate count and complexity, there will be a split in the greater than 100K gate FPGA market: Designs will be implemented in "pure" FPGAs, and designs will be implemented in system level integration chips, where 80-90% of the logic will be "fixed", and 10-20% of the design will be programmable (FPGA). The benefits of this later approach are much faster compile times, significantly improved silicon efficiency, higher performance designs and much lower cost per gate. Essentially the user will get the combined benefits of gate array cost and speed with the flexibility and reduced design risk benefits of FPGAs. Such devices are already in design today and will become common place in the near future. The design tools required to develop such devices are based on existing capabilities. Certain new tools, specifically in the are of co-verification, will be required to develop microcontroller & FPGA combined products. Such tools will be available by the middle of 1999.

Figure 14