Introduction One day in New Orleans was enough to remind me of one of the reason I moved from New Jersey to the Bay Area. The impression one gets at DAC is, of course, dependent on the people that you visit with and the sessions you attend. The topics that I found most pervasive at the conference were system-on-a-chip (SoC), verification, and the use of the Internet to serve the design engineer. There was also a fair amount of attention being paid to system-level design languages and approaches - especially those that could be directly synthesized to RTL.

There was little in the SOC area that could be related to programmable logic, except for helping with the verification problem, which I will discuss later. The one related item was the announcement by Lucent that the embedded Chip Express programmable gate array core, or CX-Core, for ASICs is now generally available. The key attribute of this approach is that designers can use already-proven standard-cell blocks and put new functions into the CX-Core programmable gate array to achieve an iterative and incremental product development methodology. This is one of the techniques available for platform-based (a new bit of jargon for the ASIC industry) SoC designs.

Platform-based design brings the same benefits as, and is not too different from rapid prototyping. It allows verification at the system level and provides a vehicle for software development. Another important benefit is that the resulting prototype is usually small enough to permit field deployment and testing.

The first announced attempt to use the CX-Core technique was Lucent's Sceptre 3 system platform for Phase 2+ Global System for Mobile (GSM) communications and third-generation (3G) wireless telephone handsets. This programmable system-on-a-chip platform, which also includes a microcontroller, digital signal processor, flash and read-only memory blocks, has up to 250K laser-programmable gates. The part is programmed by Chip Express to implement the user's logic design. The laser programming step can be replaced by a single mask process for moderate-size production runs.

CX-Core libraries are now available in Lucent's COM-1 0.25-micron modular CMOS process, and will be distributed in the pending release of Lucent's ADS 7.0 design kit. Work is under way to extend the capability to Lucent's COM-2 0.16-micron process.

Verification/Debugging

The number of verification/debugging EDA tools, equipment, and panel discussions attest to the pervasiveness of this problem. The effort and time expended when using conventional simulation techniques grows as some power of the number of gates in the design. It is not unusual for the verification/debugging process to consume 70% of a project's resources. One horror story is that Sun spends one month on a farm of 2,000 servers doing regression analyses on its chip designs.

Emulation is one approach towards easing this problem. Quickturn Design (now part of Cadence) introduced the first emulation system and was followed by IKOS, Aptix, Mentor, Axis Systems, and Simutech. FPGAs play a major role in these systems, which typically use the latest and largest FPGAs available. Aptix, for example, was among the first user of the Xilinx's large Virtex devices. Drawbacks of the gate-level emulators are the amount of effort required to partition the design into multiple FPGAs and the relatively slow operating speed - operation at less than 1MHz is not unusual. These low speeds also slow the development of the related software for these systems.

Companies, such as Aptix and Simutech, are taking advantage of the larger FPGAs now available to develop a block-based prototyping methodology. Simutech prefers to refer to its new RAVE system as a prototyping vehicle, rather than an emulator. The line between traditional emulation and the block-based approach is somewhat blurred and depends on the amount of logic placed in each FPGA.

The block-based prototypes from Aptix and Simutech are structured so that they can use standard parts and/or bonded-out IP cores in addition to the custom logic implemented in large FPGAs. As a result, these can be run at significantly higher frequencies than gate-level emulators; quite often at speeds approaching system operating requirements. Aptix, for example, claims operating speeds of 20 to 35MHz for its block-based prototypes.

The techniques being adopted by Aptix and Simutech certainly fit within the platform-based approach to SoC design. Several of the ASIC companies, like Lucent, are also moving in this direction. VLSI Technology's Velocity Rapid Silicon Prototyping product is another example. Motorola and TI are developing similar breadboard-style offerings.

It is highly likely that more than one FPGA will be required to construct the prototype. This will almost certainly be the case if several soft/firm IP cores are to be placed in the FPGAs. Partitioning of the design will required for multiple FPGA prototypes. The trick is to partition the design in such a manner as to maintain system speed and to minimize the number of interconnections between the parts.

Synplicity, at DAC, introduced a tool aimed specifically at FPGA partitioning. The Certify product actually combines the synthesis and partitioning steps in a single tool. With the partition-driven synthesis approach, the decisions made during synthesis are based on understanding the defined partition. Automatic time budgeting across multiple FPGAs is a feature of the tool. The output from Certify is a net list for the board and net lists for each of the FPGAs.

The first version of Certify works with Aptix's Explorer system and the two companies are in the process of developing a joint marketing agreement. The next release of Certify will contain interfaces to board-design and board-layout software packages.

The Internet

The Internet has rapidly become a popular design aid for the engineer. A survey conducted by Cahners found that 95% of the engineers have access to the Internet and spend an average of 13.4 hours per week online. In addition 70% have a company Intranet. Of the designers using the Internet; 86% rely on it for design ideas and tips; 88% for technical information; and 65% for comparing and choosing products.

Xilinx is already providing a no-cost design service for its CPLDs over the Internet. The company recently upgraded its Silicon Xpresso design system with the WebFITTER tool that incorporate technology acquired from MINC/Synario. The WebFITTER tool allows designers to submit any VHDL, Verilog, ABEL, EDIF or XNF file for an evaluation. Designers can target their design specifically by density, package, speed, and voltage or choose the automatic device selection feature. Utilization and timing reports, data sheets, and instant price quotes are provided on-line. For further verification, the WebFITTER tool provides HDL timing simulation models as well as a JEDEC programming file. All of the reports, timing models, and device and programming files are available for immediate download.

OrCAD is developing its no-cost activeparts.com program, which will contain an online component database. Parts can be dragged-and-dropped from this catalogue directly into an active design. The current catalogue contain 400K parts and additional parts are being added at a rate of 100K per month. OrCAD is partnering with VEBA Electronics, which claims to be the third largest component distributor. The companies are developing the infrastructure required to allow the designer to directly place orders for components and access kitting services for prototypes. The Internet is providing EDA tool vendors with the opportunity to evaluate the charge-per-use business model. Avant! claims to be the first with its edamall.com site. The company is offering two tools - Nova-Verilint and Nova-VHDLint - that it acquired with its purchase of interHDL. Users can buy tokens, at $10 each, and use the token to download either tool for one session. The company does not plan to offer its physical design tools for session-based licensing until it evaluates the results of the current effort.

Reflex Networks demonstrated an internet-based FPGA design system that it intends to develop and charge for on a per-use basis. The company has not yet set any prices for the service. Its demonstration used FPGA Express and Lucent's ORCA foundry. The same user interface was presented as when the tools are run locally. Java-enabled versions of FPGA Express and ORCA were integrated into the Reflex Networks design platform and demonstrated at DAC.