Technical Marketing, Exemplar Logic

An incremental synthesis to place and route methodology can be used to reduce the design cycle time for Xilinx FPGAs. Small functional changes can be quickly incorporated into a design after place and route while preserving timing using LeonardoSpectrum and Alliance Series. This methodology requires both the Alliance Series guide file and LeonardoSpectrum hierarchy management and incremental synthesis capabilities. Guide files can be used from previous Alliance Series place and route executions to improve place and route run times and preserving timing from the previous routes. LeonardoSpectrum Level 3 provides the necessary hierarchy control and incremental re-optimization capabilities necessary to accommodate this methodology.

Flattening or arbitrarily changing hierarchical boundaries will not accommodate a incremental synthesis and guided place and route flow. However, the ability to create and remove hierarchical boundaries will be crucial to achieving high performance while maintaining hierarchy. LeonardoSpectrum supports group and ungroup commands that can be used to manipulate hierarchy in this manner.

Guided P&R has been available within the Xilinx tool-set for some considerable time. In the early days of design capture where everything was schematic-based, guided P&R was easily achieved. This is primarily because every instance and net is drawn by the design engineer and uniquely named, either explicitly, or automatically. The current M1 tools have a capability such that the design engineer can specify a previous map and P&R .ncd file as a guide for future implementations. The Xilinx floor planner can be extremely useful to the engineer as a previous floor plan can also be used in incremental P&R. Guided P&R relies on certain properties in the net-list, specifically:

• Node, net, and instance names must be preserved where possible

• Connectivity of routing must be preserved where possible

In such circumstances, completely matching instances can immediately be placed in the previous position given in the guide files. This accelerates iterative run-times enormously and also has the benefit of preserving hand placement that may have been done in order to achieve stringent I/O timing or high internal performance. The Xilinx Design Manager provides an easy menu-driven system of specifying guide files.

The process of only changing what needs to be changed is an accepted methodology for ASIC development. Having completed the entire chip layout, the design team does not go off and re-synthesise the whole design just because a minor state-machine had to be changed to cope with an omission or design amendment. Nor do they implement flat. Re-spinning an entire layout of the silicon is also undesirable, leading to an increase in time-scales that is usually unacceptable.

The concept of incremental synthesis is remarkably simple and straightforward yet requires unique net-list and database handling in conjunction with hierarchy manipulation capabilities. While these features and capabilities are common currency for workstation-based ASIC synthesis they are only available to FPGA designers on the PC desktop in the form of Leonardo Spectrum from Exemplar Logic. Incremental synthesis fits well with the concept of bottom-up ASIC methodologies where the designer synthesizes small blocks of a complete design one block at a time. The essence of incremental synthesis is to take an existing previously synthesized net-list and simply switch out the existing entity/architecture or module for a newly written or edited one.

LeonardoSpectrum’s hierarchical database allows designers to replace a single block in the design while maintaining the optimized netlist for all remaining blocks. Without this functionality incremental synthesis and guided place and route would not be possible.

By limiting changes to the block level the remainder of the design is immune to changes introduced during the synthesis process. By simply replacing the old block with a new one, the engineer gains some significant benefits:

• Complete re-synthesis is unnecessary, making the design immune to changes in the synthesis process
• Iterative synthesis times are reduced by only recompiling changed blocks
• Team-based synthesis and development becomes easy to manage
• IP integration, whether net-list or RTL is easily and safely achieved
• Guided P&R can reduce the next P&R iteration by a considerable amount

The replacement of an internal block requires that synthesis be performed in a macro mode such that IO buffers and any output flip-flops are not created or inferred. For the 4000x and Spartan families, it is also necessary to be able to extract the GSR (if appropriate) and delete the resulting STARTUP block from the net-list. This must be done to ensure that the resulting changed net-list does not contain multiple instances of a STARTUP block, of which there can be only one. This is simply achieved in Leonardo Spectrum by setting the internal variable delete_startup to TRUE rather than the default value FALSE. Leonardo Spectrum also provides an explicit method of specifying the GSR explicitly to cover the case of multiple asynchronous resets. Both of these features ensure that the same RTL code can be used irrespective of the context in which it is used. Other synthesis tools of inferior capability frequently require re-writing of the RTL code leading to opportunities for error.

Using LeonardoSpectrum a hierarchical design can be synthesized and optimized with hierarchy preserved. The final results can be saved as both EDIF and "xdb" netlist formats. "xdb" is the native database format for LeonardoSpectrum. The following script highlights the initial design process:

The "xdb" netlist can then be loaded back into LeonardoSpectrum to restore the original design. Once restored, any of the sub-blocks can then be re-synthesized and re-optimized as a separate block then incorporated into the top-level netlist. The following script highlights the incremental optimization process:

Supporting an incremental design process is a key component of successful design of large Virtex FPGAs. The investment spent in time and effort to achieve final chip timing through the synthesis and place and route is not lost when a last minute change is required. LeonardoSpectrum’s incremental capabilities facilitate this methodology.