Introduction

FPGAs have become an integral part of the digital design toolbox because of the reprogrammablity and flexibility they afford. Designers will easily find an FPGA that meets the need for high gate count, or superior performance, or low power consumption, or minimal cost. While most FPGAs optimize one or two of these traits, its difficult to find a device that optimizes them all. When that is the case, conversion to an ASIC device is the logical alternative. This article discusses the tradeoffs that a designer needs to balance when weighing different FPGAs against a migration to an ASIC.

The term FPGA (field programmable gate array) is often used to refer to all programmable logic devices (PLDs). However there are many different PLD, CPLD (complex PLD) and FPGA architectures. In this article we will discuss the leading CPLD and FPGA architectures as well as key features of gate array and standard cell ASICs (application specific integrated circuits).

Macro-Cell Architecture

PLDs and CPLDs use a macro-cell architecture which employs a programmable AND-OR plane feeding into a flip-flop and an I/O cell. By De Morgan's theorem, all combinational logic can be reduced to a sum-of-products implementation. This architecture works well in finite state machine control-logic applications but is limited by the fact that each flip-flop requires an I/O pin. This restricts the gate count to the available packaging technology. This architecture does not work well in arithmetic circuits where carry-logic resources are needed, that is to say, when there is more than one function output per macro-cell.

In theory, the AND-OR plane is capable of supporting a very large number of gates. Except for the case of large state machines, most of the AND-OR plane gates are typically unused, making the overall gate utilization very low. When we estimate macro-cell conversions to ASICs, we usually figure no more than 20 ASIC 2-input NAND gate equivalents per macro cell (the AND-OR plane, flip-flop and I/O cell combined). Thus a typical 128 macro-cell CPLD conversion will weigh in at less than 3,000 ASIC gates -- a very small device indeed.

Lookup Table Architecture

The most common FPGA architecture combines a lookup table (LUT) function generator coupled with a flip-flop to form a logic cell. These logic cells are often grouped into small blocks of 2 or 4 cells along with special carry-logic circuits. The blocks are arrayed along with programmable routing channels and surrounded with a programmable I/O ring. The lookup tables typically accept four inputs and produce a single output. This approach allows any arbitrary function of four inputs to be loaded in as a truth table. Unlike the macro-cell approach, the logic cells are not committed to I/O pins, thus permitting much higher gate counts. Modern LUT devices support both finite state machine control-logic and arithmetic circuits very well.

While in theory the LUT architecture should be capable of supporting a large number of gates, in practice there are obstacles to utilizing all the available resources. For example, in designs that are rich with registers, the LUTs are largely empty, whereas in designs that are heavy with combinational logic, the LUTs are full -- but the flip-flops are underutilized. Depending on the extra features included in a specific FPGA family, a good rule of thumb is that there will be between seven- and 15 ASIC 2-input NAND gate-equivalents per logic cell. Thus an FPGA with 5,000 logic cells, such as the Altera APEX 20K100, FLEX 10K100, Xilinx Virtex XCV300 or XC4085, will convert to about 50,000 ASIC logic gates.

Other FPGA Architectures

Other FPGA architectures include logic cell primitives, configured in various ways, which attempt to offer better utilization of the programmable resources. These include the MUX-based logic cells used by Actel, and a rather complex but efficient logic cell used by QuickLogic. Similar to the LUT architecture, the logic cells are arrayed along with programmable interconnect and a programmable I/O ring.

Memory

System-on-chip designs require significant amounts of on-board memory. As a result, most new FPGAs now include RAM. Xilinx initially used LUTs as RAM, providing a large number of small 16-bit RAMs. Altera countered by embedding efficient custom 2 Kbit RAM blocks in the FPGA design. The RAM content continues to grow with each new FPGA product announcement.

When converting memory to an ASIC, three different approaches are commonly used. After the logic is converted to a gate array ASIC, if there is sufficient room left in the array, the array transistors are programmed as RAM. This is not efficient, but practical. If the RAM is too big for the array, then other approaches can be used, such as embedding a custom RAM block into the gate array core; or switching to a standard cell based ASIC, where logic and custom RAM blocks can be freely mixed. The approach that gives the lowest overall cost is normally used.

In terms of silicon area devoted to memory, the Altera APEX and Xilinx Virtex FPGAs now contain about twice as much RAM as logic. This explains why the "system" gate count numbers are very large even though their logic gate capacity has not grown much over previous generations.

Performance

The three important performance metrics are propagation delay (Tpd), clock-to-out delay (Tpco) and maximum clock frequency (Fmax). The CPLD architectures offer the best performance in all three areas. They do this by using sense-amplifier technology in the AND-OR plane along with fixed interconnect so that the delays are predictable. In these circumstances, gate capacity is limited. That means that for a large, high-speed design, it is necessary to use many devices.

The FPGA architectures have optimized Tpco to some extent, but Fmax and Tpd always suffer from very slow interconnect delays. Two different approaches to interconnect are in use. The segmented routing approach popularized by Xilinx consists of routing channels with short wire segments connected by programmable switch matrices. Segmented routing offers fast speeds on short connections, but poorer performance as the number of segments increases. The performance hit is offset to some extent by the availability of some long wire segment resources. Since the designer doesn't always know or control which resources are used, the delays are essentially unpredictable.

The continuous interconnect scheme popularized by Altera consists of long, equally sized wires that span the chip. This approach results in more predictable and placement-independent delays.

During conversion to an ASIC, all programmable interconnect structures are removed and the best possible performance is attained. Because wire delays are less predictable, ASIC vendors use sophisticated timing driven layout and accurate delay extraction tools to insure proper timing.

Power Consumption

Power consumption can be a critical factor in some systems, especially battery- powered applications. With the clock running, the device will draw dynamic power in proportion to the clock frequency and the amount of internal capacitance, which must be charged and discharged. Even with the clock stopped, a device will draw some amount of static power due to transistor leakage and any DC bias circuits that may be present.

Fast CPLD architectures have very high static power consumption due to the use of sense- amp technology. On the other hand their dynamic power consumption is relatively low due to their optimized interconnect schemes.

FPGA architectures generally do not employ significant DC bias circuitry and have low static power consumption. Their dynamic power consumption is relatively high, however, due to the large interconnect capacitance. The segmented interconnect scheme fairs better than does continuous interconnect as seen in the graph. ASIC devices do not use DC bias schemes and implement fully optimized interconnect, resulting in power consumption which is an order of magnitude lower than FPGAs. In many applications, this is the main reason for converting to an ASIC.

The benefits of reducing power consumption include smaller power supplies, simplified thermal management, and even reduced package weight, as ASIC packages don't need those copper heat slugs.

Timing Models

With designs getting larger and larger, FPGA vendors are all talking about the importance of simulation. In the past, however, FPGA vendors shunned simulation and espoused the try-it-and- see-if-it-works approach, thereby leaving themselves several generations behind ASIC vendors in terms of accurate device modeling. Years ago, ASIC vendors faced the deep sub-micron delay modeling problem and have come up with very accurate models. The FPGA vendors, meanwhile, are still using primitive delay models, which don't model the device accurately enough to verify tricky asynchronous circuits.

Consequently, it's best for designers working with CPLDs and FPGAs to stay with the synchronous design style so their simulations will be less susceptible to modeling error. If such a design is converted to an ASIC, the designer's test bench can be applied to the ASIC and the performance will be accurately modeled, giving extra confidence for a successful conversion.

Device Availability

CPLD and FPGA vendors strive to support customers over a wide range of applications. Their catalogs sport a range of device families with every possible combination of features, packages, and performance options. The question is whether any given configuration has ever been actually assembled, and if it has, if it was only a single lot built for a customer prototype. The answer can be critical once a production parts order is being considered. Out-of-stock FPGA parts have long lead times, typically longer than ASIC lead times. The prevailing advice is to stay with the most common CPLD or FPGA configuration in a device family.

There are also hidden pitfalls for designers who require the fastest speed grades. The fastest CPLD and FPGA parts are often very hard to obtain either due to processing problems or high demand, and are frequently reserved for key customers. On the other hand, ASICs are built to a performance spec and all the parts work to that spec.

Cost Tradeoffs

CPLD, FPGA, and ASIC piece prices depend on three factors: silicon cost, package cost and non-recurring engineering (NRE) charges. Generally the larger the CPLD or FPGA device gate count, the larger the difference in price between CPLDs and FPGAs and ASICs.

Package costs are about the same. CPLDs and FPGAs don't have NREs, ASICs do. Since the NRE must be amortized across the total number of devices, ASIC devices become cost effective at larger quantities.

Differences in the amount of silicon required and NRE costs are the most important. The silicon die photos illustrate that ASICs consume significantly less silicon area, one of the biggest reasons they cost less.

Additional cost savings can be realized if the ASIC is placed in a smaller package. This often happens when a design has a high gate count, but low I/O count, forcing the designer to use a large FPGA package configuration. By planning ahead, the board can be designed to accept two package foot prints.

The NREs for an FPGA-to-ASIC migration or CPLD-to-ASIC migration typically run $20,000 to $40,000. This adds $2 to $4 to the piece price at 10,000 units, but only $0.20 to $0.40 at 100,000 units. The next chart shows the relationship between price and volume for a common FPGA to ASIC conversion.

Another conversion issue commonly overlooked in a cost analysis is on-board EPROMs. When EPROMs are included in a design, there are additional unit costs, board space costs, and programming expenses.

Product Lifetime Considerations

A key selling point of FPGA technology is flexibility. However, once a design is complete, you may need to be able to buy the same part for many years. Unfortunately, in the race to advance CPLD and FPGA technology, vendors are migrating or obsoleting older products at an accelerated rate.

In the migration business, we see CPLD and FPGA consumers scrambling to find replacement parts. Often it's hard to find a part with the same package and pinout, especially with respect to power and ground connections. ASIC migration services can address these problems by providing drop-in replacement parts. Some ASIC vendors support old ASIC manufacturing process recipes for years by adapting the old process flows to new equipment.

System Considerations

CPLDs address high-performance, low gate-count applications. FPGAs support higher gate- count, but slower applications, and those applications that require RAM. ASICs offer true system- on-a chip solutions, combining performance, gate count capacity, abundant RAM as well as packaging alternatives.

ASIC technology also supports a wide range of IP cores with ease. Whereas IP for FPGAs must often use fixed placement, that same IP can be directly transferred to an ASIC and take advantage of the increased performance without having to worry about placement. The best advice in purchasing IP is to always purchase it from a third party alliance partner so that an ASIC license can be obtained.

Conclusion

The material presented here should help you select the appropriate CPLD or FPGA architecture for your application, as well as give you insight into the FPGA-to-ASIC migration process.

FPGAs make wonderful prototyping vehicles for a wide range of applications. However if your system requires gate count, performance, power consumption and cost goals that cannot be met by off-the-shelf CPLDs or FPGAs, then you should consider converting to an ASIC.

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